公开(公告)号：WO1984001471A1

公开(公告)日：1984-04-12

申请号：PCT/US1983001505

申请日：1983-09-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WOLLESEN, Donald, L. ,  SANDER, Craig, S. ,  HASKELL, Jacob, D.

IPC: H01L23/48

CPC classification number: H01L23/53223 ,  H01L21/76889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for integrated circuits having a layer of aluminum (16) and a layer of refractory metal silicide (17) on the aluminum layer (16) to form an aluminum-silicide composite layer. Ranges of suitable thicknesses for the aluminum and metal silicide layers are disclosed. Molybdenum (Mo) and tantalum (Ta) may be used as the refractory metal in the metal silicide layer. Also disclosed is a method of manufacturing an interconnect structure in an integrated circuit providing a first insulating layer (12) over a semiconductor substrate having a plurality of active regions (11) at the surface of the semiconductor substrate (10), forming a first aluminum layer (16) over the first insulating layer (12), forming a metal silicide layer (17) over the aluminum layer (16), and selectively removing parts of the first aluminum layer (16) and the metal silicide layer (17) in a predetermined pattern whereby an aluminum-metal silicide interconnect structure is formed coupling at least some of the active regions (11).

Abstract translation: 一种用于在铝层（16）上具有铝层（16）和难熔金属硅化物层（17）的层的集成电路的互连结构，以形成铝硅化物复合层。 公开了铝和金属硅化物层的合适厚度的范围。 钼（Mo）和钽（Ta）可以用作金属硅化物层中的难熔金属。 还公开了一种在集成电路中制造互连结构的方法，该集成电路在半导体衬底上提供了在半导体衬底（10）的表面上具有多个有源区（11）的半导体衬底上的第一绝缘层（12），形成第一铝 在所述第一绝缘层（12）上形成层（16），在所述铝层（16）上形成金属硅化物层（17），并且选择性地去除所述第一铝层（16）和所述金属硅化物层 形成耦合至少一些有源区（11）的铝 - 金属硅化物互连结构的预定图案。

公开(公告)号：WO1989005519A1

公开(公告)日：1989-06-15

申请号：PCT/US1988004290

申请日：1988-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HASKELL, Jacob, D.

IPC: H01L21/90

CPC classification number: H01L21/76897 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel process is provided to fabricate interconnections (46c) in transistors (14) having self-aligned, planarized contacts (46s, 40g, 46d) in a novel, completely self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 mu m and lower. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N+ and p+ polysilicon plugs.

公开(公告)号：WO1989005516A1

公开(公告)日：1989-06-15

申请号：PCT/US1988004291

申请日：1988-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HASKELL, Jacob, D.

IPC: H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/28525 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel process is provided for fabricating transistors (14), contacts (46s, 40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 mu m and lower. In a preferred embodiment, the configuration is also planarized. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N and P polysilicon plugs.

Abstract translation: 提供了一种以新颖的自对准配置制造晶体管（14），触点（46s，40g，46d）和互连（46c）的新颖工艺。 本发明的方法允许更高的包装密度，并且允许特征距离接近0.5μm和更低。 在优选实施例中，该配置也被平坦化。 结合在半导体晶片（16）的表面上形成的多层结构（28）的掩模的独特组合，其中包括其中的掩埋蚀刻停止层（28b）的多层结构限定了源（18） ），栅极（22）和漏极（20）元件及其相对于彼此的几何形状并互连。 多晶硅插头（40,46）通过多结构层中的狭槽接触允许对各种元件进行垂直接触。 多晶硅插塞的硅化（56）降低了垂直方向上的串联电阻，并允许N +和P +多晶硅插头的捆扎。

公开(公告)号：WO1989005517A1

公开(公告)日：1989-06-15

申请号：PCT/US1988004292

申请日：1988-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HASKELL, Jacob, D.

IPC: H01L21/28

CPC classification number: H01L21/76889 ,  H01L21/28525 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel process is provided for fabricating contacts (46s, 40g, 46d) in a novel, completely self-aligned, planarized configuration for transistors (14), with self-aligned interconnections (46c). The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 mu m and lower. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N and P polysilicon plugs.

Abstract translation: 提供了一种用于以具有自对准互连（46c）的晶体管（14）的新颖的，完全自对准的平面化配置来制造触点（46s，40g，46d）的新颖工艺。 本发明的方法允许更高的包装密度，并且允许特征距离接近0.5μm和更低。 结合在半导体晶片（16）的表面上形成的多层结构（28）的掩模的独特组合，其中包括其中的掩埋蚀刻停止层（28b）的多层结构限定了源（18） ），栅极（22）和漏极（20）元件及其相对于彼此的几何形状并互连。 多晶硅插头（40,46）通过多结构层中的狭槽接触允许对各种元件进行垂直接触。 多晶硅插塞的硅化（56）降低了垂直方向上的串联电阻，并允许N +和P +多晶硅插头的捆扎。

公开(公告)号：EP0344292B1

公开(公告)日：1997-04-23

申请号：EP89900987.2

申请日：1988-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HASKELL, Jacob, D.

IPC: H01L21/28 ,  H01L23/50

CPC classification number: H01L21/76877 ,  H01L21/28525 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel process is provided for fabricating transistors (14), contacts (46s, 40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 mum and lower. In a preferred embodiment, the configuration is also planarized. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N+ and P+ polysilicon plugs.

公开(公告)号：EP0120918A1

公开(公告)日：1984-10-10

申请号：EP83903284.0

申请日：1983-09-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WOLLESEN, Donald, L. ,  SANDER, Craig, S. ,  HASKELL, Jacob, D.

IPC: H01L21 ,  H01L23 ,  H01L27 ,  H01L29

CPC classification number: H01L23/53223 ,  H01L21/76889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structure d'interconnexion pour circuits intégrés possédant une couche d'aluminium (16) et une couche de siliciure métallique réfractaire (17) sur la couche d'aluminium (16) de manière à former une couche composite de siliciure-aluminium. Des plages d'épaisseurs appropriées pour les couches d'aluminium et de siliciure métallique sont également décrites. Le molybdène (Mo) et le tantale (Ta) peuvent être utilisés en tant que métal réfractaire dans la couche de siliciure métallique. On décrit également un procédé de fabrication d'une structure d'interconnexion dans un circuit intégré formant une première couche isolante (12) sur un substrat semiconducteur possédant une pluralité de régions actives (11) à la surface du substrat semiconducteur (10), consistant à former une première couche d'aluminium (16) sur la première couche isolante (12), une couche de siliciure métallique (17) sur la couche d'aluminium (16), et à enlever de manière sélective des parties de la première couche d'aluminium (16) et de la couche de siliciure métallique (17) selon un motif prédéterminé, de manière à former unestructure d'interconnexion en siliciure métallique-aluminium permettant de coupler au moins quelques-unes des régions actives (11).

公开(公告)号：EP0120918B1

公开(公告)日：1991-12-18

申请号：EP83903284.4

申请日：1983-09-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WOLLESEN, Donald, L. ,  SANDER, Craig, S. ,  HASKELL, Jacob, D.

IPC: H01L23/48 ,  H01L29/46 ,  H01L29/62

CPC classification number: H01L23/53223 ,  H01L21/76889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for integrated circuits having a layer of aluminum (16) and a layer of refractory metal silicide (17) on the aluminum layer (16) to form an aluminum-silicide composite layer. Ranges of suitable thicknesses for the aluminum and metal silicide layers are disclosed. Molybdenum (Mo) and tantalum (Ta) may be used as the refractory metal in the metal silicide layer. Also disclosed is a method of manufacturing an interconnect structure in an integrated circuit providing a first insulating layer (12) over a semiconductor substrate having a plurality of active regions (11) at the surface of the semiconductor substrate (10), forming a first aluminum layer (16) over the first insulating layer (12), forming a metal silicide layer (17) over the aluminum layer (16), and selectively removing parts of the first aluminum layer (16) and the metal silicide layer (17) in a predetermined pattern whereby an aluminum-metal silicide interconnect structure is formed coupling at least some of the active regions (11).

公开(公告)号：EP0344277A1

公开(公告)日：1989-12-06

申请号：EP89900554.0

申请日：1988-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HASKELL, Jacob, D.

IPC: H01L21 ,  H01L23 ,  H01L27 ,  H01L29

CPC classification number: H01L21/76897 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel process is provided to fabricate interconnections (46c) in transistors (14) having self-aligned, planarized contacts (46s, 40g, 46d) in a novel, completely self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 mu m and lower. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N+ and p+ polysilicon plugs.

公开(公告)号：EP0368938A1

公开(公告)日：1990-05-23

申请号：EP89900750.0

申请日：1988-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HASKELL, Jacob, D.

IPC: H01L21 ,  H01L23 ,  H01L27 ,  H01L29

CPC classification number: H01L21/76889 ,  H01L21/28525 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel process is provided for fabricating contacts (46s, 40g, 46d) in a novel, completely self-aligned, planarized configuration for transistors (14), with self-aligned interconnections (46c). The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 µm and lower. A unique combination of masks in conjunc­ tion with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure includ­ ing a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain 20 elements and their geometry rel­ ative to each other and to interconnects. Polysilicon plug (40,46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N⁺ and P⁺ polysilicon plugs.

Abstract translation: 在具有自对准互连（46c）的晶体管（14）的新的完全自对准扁平配置中描述了一种新的接触制造方法（46s，40g，46d）。 本发明的方法实现更高的接触密度，并且允许特征距离接近0.5μm和更小。 形成在晶片的半导体（16）的表面上设置有多层结构相关联的掩模的一个独特的组合（20），所述多层包括一个掩埋层停止所述蚀刻结构（28B）限定了源元件（ 18），栅极（22）和漏极（20）及其几何形状相对于彼此以及相对于互连。 穿过多层结构中的槽的多晶硅引脚触点（40,46）提供与各种元件的垂直接触。 多晶硅插塞的硅化物（56）降低了垂直方向上的串联电阻并允许多晶硅插塞N +和P +的连接。

公开(公告)号：EP0344292A1

公开(公告)日：1989-12-06

申请号：EP89900987.0

申请日：1988-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HASKELL, Jacob, D.

IPC: H01L21 ,  H01L23 ,  H01L27 ,  H01L29

CPC classification number: H01L21/76877 ,  H01L21/28525 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A novel process is provided for fabricating transistors (14), contacts (46s,40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature dis­ tances to approach 0.5 µm and lower. In a preferred embodiment, the configuration is also planarized. A unique combina­ tion of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) ele­ ments and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N⁺ and P⁺ polysilicon plugs.