公开(公告)号：WO1998018080A1

公开(公告)日：1998-04-30

申请号：PCT/US1997019059

申请日：1997-10-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HELMS, Frank, P.

IPC: G06F13/40

CPC classification number: G06F13/4063 ,  G06F13/4068

Abstract: A Peripheral Component Interconnect (PCI) compatible peripheral device for coupling to a PCI bus, the peripheral device comprising a primary function component and a connection portion. The primary function includes a PCI interface for coupling to the PCI bus, and a primary configuration space coupled to the PCI interface and accessible by the PCI bus via the PCI interface. The connection portion is coupled to the primary function component and supports a secondary function component. The primary function component provides PCI bus access via the PCI interface to the secondary function component when the secondary function component is coupled to the connection portion. The primary function component provides PCI bus access via the PCI interface to a secondary configuration space when the secondary function component is coupled to the connection portion.

Abstract translation: 一种用于耦合到PCI总线的外围组件互连（PCI）兼容的外围设备，所述外围设备包括主要功能部件和连接部分。 主要功能包括用于耦合到PCI总线的PCI接口和耦合到PCI接口的主要配置空间，并可通过PCI接口由PCI总线访问。 连接部分耦合到主要功能部件并且支持辅助功能部件。 当辅助功能组件耦合到连接部分时，主要功能部件通过PCI接口将PCI总线接入辅助功能组件。 当辅助功能组件耦合到连接部分时，主要功能部件通过PCI接口将PCI总线访问提供给辅助配置空间。

公开(公告)号：WO2008143980A2

公开(公告)日：2008-11-27

申请号：PCT/US2008/006294

申请日：2008-05-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  BRANOVER, Alex ,  HELMS, Frank, P. ,  OWEN, Jonathan, M. ,  LEWCHUK, Kurt ,  STEINMAN, Maurice ,  MACKEY, Paul

Inventor： BRANOVER, Alex ,  HELMS, Frank, P. ,  OWEN, Jonathan, M. ,  LEWCHUK, Kurt ,  STEINMAN, Maurice ,  MACKEY, Paul

IPC: G06F1/32

CPC classification number: G06F1/3203

Abstract: A processor (105) can operate in different power modes. In an active power mode, the processor executes software (303). In response to receiving a halt indication (304) from the software, hardware at the processor evaluates bus transactions (306) for the processor. If the bus transactions meet a heuristic (307), hardware places a processor core in a lower power mode, such as a retention mode (308). Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

Abstract translation: 处理器（105）可以以不同的功率模式操作。 在有功功率模式下，处理器执行软件（303）。 响应于从软件接收到停止指示（304），处理器处的硬件评估处理器的总线事务（306）。 如果总线事务满足启发式（307），则硬件将处理器核放置在较低功率模式（例如保留模式（308））中。 由于总线事务由硬件而不是软件进行评估，并且软件不需要执行握手和其他协议来将处理器置于低功耗模式，处理器能够将处理器内核置于低功耗模式 更快，从而节约电力。

公开(公告)号：WO2008137079A2

公开(公告)日：2008-11-13

申请号：PCT/US2008/005692

申请日：2008-05-02

Applicant: ADVANCED MICRO DEVICES, INC. ,  BRANOVER, Alex ,  HELMS, Frank, P. ,  STEINMAN, Maurice

Inventor： BRANOVER, Alex ,  HELMS, Frank, P. ,  STEINMAN, Maurice

CPC classification number: G06F1/324 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions (402). In a low-power mode, a retention voltage is provided to the processor (408). The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode (412).

Abstract translation: 处理器可以在三种不同的模式下工作。 在主动模式中，向处理器提供第一电压，其中第一电压足以允许处理器执行指令（402）。 在低功率模式下，向处理器（408）提供保持电压。 处理器在保留模式下的功耗比活动模式低。 此外，处理器可以在第三模式下操作，其中向处理器提供足够的电压以允许处理器处理诸如一致性消息之类的缓存消息，但不执行其他正常操作或以非常低的速度执行正常操作 相对于它们在活动模式下的性能（412）。

公开(公告)号：WO1998016999A1

公开(公告)日：1998-04-23

申请号：PCT/US1997019060

申请日：1997-10-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HELMS, Frank, P.

IPC: H03G03/32

CPC classification number: H03G3/32

Abstract: A system and method for automatically adjusting the volume of an audio system to compensate for variations in ambient noise. The system includes a microphone for monitoring the ambient audio environment which includes output of the audio system plus environmental noise. The system also includes processing circuitry connected to the microphone. The processing circuitry varies the volume of the output of the audio system in proportion to changes in the environmental noise. The processing circuitry comprises the microphone, located to detect the ambient sound in the listening environment, an analog-to-digital converter connected to the output of the microphone, and a digital signal processor connected to the output of the analog-to-digital converter. The output signal of the DSP is an input to the volume control of the audio system.

Abstract translation: 一种用于自动调整音频系统音量以补偿环境噪声变化的系统和方法。 该系统包括用于监视环境音频环境的麦克风，其包括音频系统的输出以及环境噪声。 该系统还包括连接到麦克风的处理电路。 处理电路根据环境噪声的变化来改变音频系统的输出音量。 所述处理电路包括所述麦克风，所述麦克风位于用于检测所述聆听环境中的环境声音，连接到所述麦克风的输出的模拟数字转换器以及连接到所述模数转换器的输出的数字信号处理器 。 DSP的输出信号是音频系统音量控制的输入。

公开(公告)号：EP1309909A2

公开(公告)日：2003-05-14

申请号：EP01935179.0

申请日：2001-05-09

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HELMS, Frank, P.

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/28

Abstract: Disclosed herein are a method and apparatus to provide a deterministic power-on voltage in a system having a processor-controlled voltage level. In one embodiment, the system includes a DC/DC converter, a processor, and a selection circuit. The DC/DC converter receives a voltage setting signal or signals from the selection circuit and provides an adjustable power output signal having a voltage indicated by the voltage setting signal. The processor is powered by the adjustable power output signal. When powered, the processor provides a programmable voltage setting signal or signals. The selection circuit receives the programmable voltage setting signal or signals, a hardwired voltage setting signal, and a selection signal or signals, and when the selection signal is in a predetermined condition, the selection circuit provides the programmable voltage setting signal or signals from the processor to the DC/DC converter. Preferably, when the selection signal is in a second predetermined condition complementary to the first predetermined condition, the circuit provides the hardwired voltage setting signal to the DC/DC converter. The first and second predetermined conditions of the selection signal are preferably de-assertion and assertion, respectively. The selection signal may be determined by a logic gate that combines a mode control signal and a power good signal, and causes the selection signal to select the voltage setting signal from the processor only when the power good signal is asserted and the mode control signal is de-asserted. This advantageously allows for the processor to dictate its operating voltage level, and ability that is extremely useful for power and thermal management in notebook PCs.

公开(公告)号：EP1309909B1

公开(公告)日：2008-03-19

申请号：EP01935179.0

申请日：2001-05-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HELMS, Frank, P.

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/28

Abstract: Disclosed herein are a method and apparatus to provide a deterministic power-on voltage in a system having a processor-controlled voltage level. In one embodiment, the system includes a DC/DC converter, a processor, and a selection circuit. The DC/DC converter receives a voltage setting signal or signals from the selection circuit and provides an adjustable power output signal having a voltage indicated by the voltage setting signal. The processor is powered by the adjustable power output signal. When powered, the processor provides a programmable voltage setting signal or signals. The selection circuit receives the programmable voltage setting signal or signals, a hardwired voltage setting signal, and a selection signal or signals, and when the selection signal is in a predetermined condition, the selection circuit provides the programmable voltage setting signal or signals from the processor to the DC/DC converter. Preferably, when the selection signal is in a second predetermined condition complementary to the first predetermined condition, the circuit provides the hardwired voltage setting signal to the DC/DC converter. The first and second predetermined conditions of the selection signal are preferably de-assertion and assertion, respectively. The selection signal may be determined by a logic gate that combines a mode control signal and a power good signal, and causes the selection signal to select the voltage setting signal from the processor only when the power good signal is asserted and the mode control signal is de-asserted. This advantageously allows for the processor to dictate its operating voltage level, and ability that is extremely useful for power and thermal management in notebook PCs.