Abstract:
A method and apparatus provides an integrated circuit device that allows for a high field threshold voltage by minimizing the parasitic transistors located therein. The integrated circuit includes a well region, a source/drain region, a nitride layer and a first oxide layer coupled to the well region. The system masks and etches a nitride layer and then provides a field implant region in the well area. Thereafter, it etches the nitride again where the field implant region is moved away from the source/drain region. In so doing, the field implant region is spaced away from the source/drain region of the device and therefore the breakdown voltage of the device is effectively increased.
Abstract:
A method and apparatus provides an integrated circuit device that allows for a high field threshold voltage by minimizing the parasitic transistors located therein. In this system, an oxide layer is provided over the transistor. The layer is then etched to the top of the nitride layer, thereby allowing oxide portions on the sides thereof to be utilized as the mask when the implant is provided. These oxide portions are utilized to space the field implant away from the source drain region of the device and therefore the breakdown voltage is effectively increased.