公开(公告)号：WO1998000863A1

公开(公告)日：1998-01-08

申请号：PCT/US1997003552

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KEPLER, Nick

IPC: H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/76834 ,  H01L21/76895

Abstract: The invention utilizes two separate LI stack depositions and etches. In the first step, a layer of oxide etch stop (24) and a layer (26) of TEOS oxide are deposited to form a first LI stack. This stac is then contact etched, filled, and polished. A second LI stack is then formed by deposition of a doped silane oxide layer (30) that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop (24), a second layer (26) of undoped TEOS oxide, and a final layer of doped silane oxide (30).

Abstract translation: 本发明利用两个独立的LI堆叠沉积和蚀刻。 在第一步骤中，沉积氧化物蚀刻停止层（24）和TEOS氧化物层（26）以形成第一LI堆叠。 然后将该stac接触刻蚀，填充和抛光。 然后通过沉积接触蚀刻，填充和抛光的掺杂硅烷氧化物层（30）形成第二个LI堆叠。 该方法产生具有第一层氧化物蚀刻停止层（24），未掺杂的TEOS氧化物的第二层（26）和掺杂的硅烷氧化物（30）的最终层的ILD。

公开(公告)号：WO1998000862A1

公开(公告)日：1998-01-08

申请号：PCT/US1997001713

申请日：1997-02-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LIU, Yowjuang, W. ,  FATEMI, Homi ,  KEPLER, Nick ,  BUYNOSKI, Matthew, S. ,  YUE, John, T.

IPC: H01L21/768

CPC classification number: H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L2221/1047

Abstract: A method of forming low dielectric constant insulation (14) between those pairs of conductive lines (12), of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a fluid material containing insulating solids, such as a silicate, and drying said fluid material at a temperature and time so as to create, in the gap (31), a microporous material containing a gas with a dielectric constant of slightly above 1 or a large void whose dielectric constant is slightly greater than 1. Preferably the insulating solid is tetraethylorthosilicate. The resultant method forms an insulating material in the gaps of the conductive lines which has porosity in the range of about 0.6/um to about 2.0/um with a pore size in the range of 25 nm to 500 nm, and the density ranges from 0.01 to about 0.8 gram/cm . The composite dielectric constant of the porous insulating material is in the range of about 1.1 to about 2.0.

Abstract translation: 一种在这些导线（12）对之间形成用于集成电路的互连级别的低介电常数绝缘（14）的方法，其具有约0.5微米或更小的间隙，通过沉积含有绝缘固体的流体材料，例如 硅酸盐，并且在温度和时间下干燥所述流体材料，以在间隙（31）中产生包含介电常数略高于1的气体的微孔材料或介电常数略大于 绝缘固体优选为原硅酸四乙酯。 所得到的方法在导电线的间隙中形成绝缘材料，该绝缘材料的孔隙率在约0.6 /μm3至约2.0 /μm3的范围内，孔径在25nm至500nm的范围内， 密度范围为0.01至约0.8克/厘米3。 多孔绝缘材料的复合介电常数在约1.1至约2.0的范围内。

公开(公告)号：EP0909461B1

公开(公告)日：2003-09-17

申请号：EP97915877.1

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KEPLER, Nick

IPC: H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/76834 ,  H01L21/76895

Abstract: The invention utilizes two separate LI stack depositions and etches. In the first step, a layer of oxide etch stop (24) and a layer (26) of TEOS oxide are deposited to form a first LI stack. This stac is then contact etched, filled, and polished. A second LI stack is then formed by deposition of a doped silane oxide layer (30) that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop (24), a second layer (26) of undoped TEOS oxide, and a final layer of doped silane oxide (30).

公开(公告)号：EP0909461A1

公开(公告)日：1999-04-21

申请号：EP97915877.0

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KEPLER, Nick

IPC: H01L21

CPC classification number: H01L21/76801 ,  H01L21/76834 ,  H01L21/76895

Abstract: The invention utilizes two separate LI stack depositions and etches. In the first step, a layer of oxide etch stop (24) and a layer (26) of TEOS oxide are deposited to form a first LI stack. This stac is then contact etched, filled, and polished. A second LI stack is then formed by deposition of a doped silane oxide layer (30) that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop (24), a second layer (26) of undoped TEOS oxide, and a final layer of doped silane oxide (30).