公开(公告)号：WO1997044734A1

公开(公告)日：1997-11-27

申请号：PCT/US1997008362

申请日：1997-05-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  QURESHI, Qadeer ,  ENNIS, Steve ,  WISOR, Michael, T.

IPC: G06F11/26

CPC classification number: G06F11/2221 ,  G06F11/22 ,  G06F11/2231 ,  G06F11/261 ,  G06F13/24

Abstract: A processing system comprising at least one processing unit, a plurality of I/O devices, and a central interrupt control unit intercoupling the processing unit and the plurality of I/O devices. The central interrupt control unit is configured to distribute said interrupt signals to the processing unit. The central interrupt control unit comprises a test mechanism that is configured to provide simulated test interrupt signals to the input channels of the interrupt controller. In a preferred embodiment the test mechanism includes a test control register to control the assertion of the simulated interrupt signals, a test stimulus register to provide the simulated interrupt signals and a test status register to receive status information relating to the central interrupt control unit's processing of the simulated interrupt signals.

Abstract translation: 一种处理系统，包括至少一个处理单元，多个I / O设备和与所述处理单元和所述多个I / O设备相互配合的中央中央控制单元。 中央中断控制单元被配置为将所述中断信号分配给处理单元。 中央中断控制单元包括被配置为向中断控制器的输入通道提供模拟测试中断信号的测试机构。 在优选实施例中，测试机构包括用于控制模拟中断信号的断言的测试控制寄存器，用于提供模拟中断信号的测试激励寄存器和用于接收与中央中断控制单元的处理有关的状态信息的测试状态寄存器 模拟中断信号。