公开(公告)号：WO1996038917A1

公开(公告)日：1996-12-05

申请号：PCT/US1996004612

申请日：1996-04-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  AGRAWAL, Om, P. ,  SHARPE-GEISLER, Bradley, A. ,  SCHMITZ, Nicholas, A. ,  MOYER, Bryon, I.

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17704

Abstract: A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchical level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.

Abstract translation: 一种非常高密度的复杂可编程逻辑器件（CPLD）具有多个层级信号路径。 层次结构的最低层次与所有更高层次是独立的。 类似地，中间级别与所有较高级别无关，并且仅利用与最低和中级层级相关联的CPLD的资源。 第一层级资源包括具有多个输入线和多条输出线的可编程逻辑块以及连接到可编程逻辑块的多条输入线的可编程块开关矩阵。 第二层级资源包括连接到可编程块开关矩阵的多个输入线的可编程段开关矩阵。 CPLD另外包括具有连接到第二层级资源的第三层级资源的第三层级电路，其中第三层级信号路径利用第三级，第二级和第一层次级资源。 第三层级资源包括可编程全局开关矩阵，其具有可编程地连接到可编程段开关矩阵的线路并与其断开的全局开关矩阵线。

公开(公告)号：WO1996038919A1

公开(公告)日：1996-12-05

申请号：PCT/US1996004858

申请日：1996-04-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  AGRAWAL, Om, P. ,  SHARPE-GEISLER, Bradley, A. ,  SCHMITZ, Nicholas, A.

IPC: H03K19/177

CPC classification number: H03K19/177 ,  H03K19/1737 ,  H03K19/17704

Abstract: A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDs and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected to an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines.

Abstract translation: 可编程优化分配逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。 可编程优化分配逻辑分配器为CPLD的每个I / O引脚提供优化数量的产品术语，并且与反馈相同的统一数量的产品术语。 然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。 可编程优化分配逻辑分配器包括多个路由器元件，其中每个路由器元件将选择数量的乘积项和项的总和从PAL结构（即选定数量的逻辑产品项集群）引导到 可编程选择逻辑宏单元。 具体地，可编程优化分配逻辑分配器具有多个输入线，多个输出线和多个可编程路由器元件。 每个可编程路由器元件具有连接到多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。