Abstract:
A novel interconnect layout method and metallization scheme is provided. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers (32, 36) stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other.
Abstract:
The present invention provides a method for fabricating small structures to be employed in integrated circuits formed on a semiconductor substrate (12). Examples of such small structures include contacts, vias, and metal lines. The method of the present invention employs an image reversal technique to obtain improved feature definition. In forming a feature (28) in a layer of material (16), a clear field reticle is used to form patterned segments of photoresist (18) each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features (28) intended to be formed in the layer of material (16). This method is employed instead of using a dark field reticle which forms windows in a photoresist each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features (28) intended to be formed in the layer of material (16). For small structures, the openings or windows in a photoresist are harder to form than the patterned segments of photoresist (18). With the method of the present invention which employs a clear field reticle to form a mask comprising patterned segments of photoresist (18), the limitations of patterning small windows in a photoresist with the use of a dark field reticle are avoided. The accuracy of forming the small structures is thus improved.
Abstract:
The present invention provides a method for fabricating small structures to be employed in integrated circuits formed on a semiconductor substrate (12). Examples of such small structures include contacts, vias, and metal lines. The method of the present invention employs an image reversal technique to obtain improved feature definition. In forming a feature (28) in a layer of material (16), a clear field reticle is used to form patterned segments of photoresist (18) each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features (28) intended to be formed in the layer of material (16). This method is employed instead of using a dark field reticle which forms windows in a photoresist each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features (28) intended to be formed in the layer of material (16). For small structures, the openings or windows in a photoresist are harder to form than the patterned segments of photoresist (18). With the method of the present invention which employs a clear field reticle to form a mask comprising patterned segments of photoresist (18), the limitations of patterning small windows in a photoresist with the use of a dark field reticle are avoided. The accuracy of forming the small structures is thus improved.
Abstract:
A novel interconnect layout method and metallization scheme is provided. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers (32, 36) stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other.
Abstract:
A novel interconnect layout method and metallization scheme is provided. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers (32, 36) stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other.
Abstract:
The present invention provides a method for fabricating small structures to be employed in integrated circuits formed on a semiconductor substrate (12). Examples of such small structures include contacts, vias, and metal lines. The method of the present invention employs an image reversal technique to obtain improved feature definition. In forming a feature (28) in a layer of material (16), a clear field reticle is used to form patterned segments of photoresist (18) each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features (28) intended to be formed in the layer of material (16). This method is employed instead of using a dark field reticle which forms windows in a photoresist each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features (28) intended to be formed in the layer of material (16). For small structures, the openings or windows in a photoresist are harder to form than the patterned segments of photoresist (18). With the method of the present invention which employs a clear field reticle to form a mask comprising patterned segments of photoresist (18), the limitations of patterning small windows in a photoresist with the use of a dark field reticle are avoided. The accuracy of forming the small structures is thus improved.