公开(公告)号：JPH04233356A

公开(公告)日：1992-08-21

申请号：JP12408691

申请日：1991-05-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： FUIRUTSUIN FUIRUUTSUMAN ,  BURAIAN CHIRUDAAZU

IPC: H04L12/42 ,  H04J3/06 ,  H04L12/433

Abstract: PURPOSE: To prevent locking-up of a single reception FIFO where data passes by controlling the flow for one queue at a time in accordance with precedence and transmitting framed data in a reception area to a network. CONSTITUTION: An output buffer 126 is provided with a reception FIFO 175 including a queue of data received from a medium and a transmission FIFO 177 including at least one queue of data to be supplied to a medium. The buffer 126 is so programmed that it has FIFOs including data queues different by priorities, and a pointer is used to perform the control. Data received from the medium is supplied to a system memory through a link list queue 178 by a network DMA controller 124. Data is transmitted to the medium through a queue 180 corresponding asynchronous priority. This transmission flow is controlled to prevent locking-up of the single FIFO where data passes.