公开(公告)号：JPH04233353A

公开(公告)日：1992-08-21

申请号：JP12617591

申请日：1991-05-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： FUIRUTSUIN FUIRUUTSUMAN ,  GURURAJI SHIN

IPC: H04B10/20 ,  H04L12/433

Abstract: PURPOSE: To improve transmission of asynchronous data in an FDDI network. CONSTITUTION: A standard FDDI precedence algorithm is executed by programming this algorithm as a function of a token hold time(THT) in the direction of THT threshold reduction or increase for asynchronous service. If it is programmed in the direction of threshold reduction, all of data having a high priority is transmitted to a network before data having a low priority is transmitted. If it is programmed in the direction of threshold increase, data having the highest priority is first transmitted and data having a low priority level is transmitted, and this operation is repeated hereafter until the token hold time which has not been expired is made shorter than the threshold for precedence. Consequently, at least several data out of all priority-assigned data pending for transmission are transmitted to a medium at the time of acquisition of each token.

公开(公告)号：JPH04233352A

公开(公告)日：1992-08-21

申请号：JP12617491

申请日：1991-05-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： FUIRUTSUIN FUIRUUTSUMAN

IPC: H04B10/20 ,  H04L12/42 ,  H04L12/56 ,  H04L29/02

Abstract: PURPOSE: To improve the throughput of framed data in a network. CONSTITUTION: Packets of data stored in transmission and reception FIFOs in a MAC 120 are classified by tag and state bits in last words of individual packets without being mutually marked. Data to be transmitted is transferred from a system memory to the transmission FIFO, and data received from a network is stored in the reception FIFO. For the purpose of maximizing the data throughput, a determined quantity of data or a complete packet is stored in the transmission FIFO, and data is transmitted to the network while data is received from the system memory. When the determined quantity of data is stored in the reception FIFO, data is transferred to the system memory while data comes from the network.

公开(公告)号：JPH04261245A

公开(公告)日：1992-09-17

申请号：JP12628591

申请日：1991-05-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： FUIRUTSUIN FUIRUUTSUMAN

IPC: G06F13/28 ,  G06F13/36 ,  H04L12/42 ,  H04L12/56 ,  H04L13/08 ,  H04L29/06

Abstract: PURPOSE: To improve data management of a buffer storage system. CONSTITUTION: Transmission and reception data are stored in a buffer area normalized by first and second memories on a network. The buffer area is instructed by multiple descriptor ring stored in the memories. In one situation, the two memories are present on different buses 143 connected with a common bus 147 including a processor 124. The processor 124 communicates with the memories by using a handshake protocol. In another situation, the received data incoming to this system are distributed among the multiple descriptor ring. Moreover, in another situation, a frame is divided among the multiple descriptor ring dependently of characteristic codes held by the frame in a frame control field. Synchronization between the header of the frame and data is maintained by the frame number of each descriptor. In another situation, the block of a reception path at the time of the generation of the blocked receiving descriptor ring is prevented.

公开(公告)号：JPH04233356A

公开(公告)日：1992-08-21

申请号：JP12408691

申请日：1991-05-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： FUIRUTSUIN FUIRUUTSUMAN ,  BURAIAN CHIRUDAAZU

IPC: H04L12/42 ,  H04J3/06 ,  H04L12/433

Abstract: PURPOSE: To prevent locking-up of a single reception FIFO where data passes by controlling the flow for one queue at a time in accordance with precedence and transmitting framed data in a reception area to a network. CONSTITUTION: An output buffer 126 is provided with a reception FIFO 175 including a queue of data received from a medium and a transmission FIFO 177 including at least one queue of data to be supplied to a medium. The buffer 126 is so programmed that it has FIFOs including data queues different by priorities, and a pointer is used to perform the control. Data received from the medium is supplied to a system memory through a link list queue 178 by a network DMA controller 124. Data is transmitted to the medium through a queue 180 corresponding asynchronous priority. This transmission flow is controlled to prevent locking-up of the single FIFO where data passes.