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公开(公告)号:JPH07295811A
公开(公告)日:1995-11-10
申请号:JP10142795
申请日:1995-04-25
Applicant: ADVANCED MICRO DEVICES INC
Inventor: JIERARUDO DEI ZURAASUKI JIYUNI , SUKOTSUTO EI HOWAITO , MIYURARI ESU CHINNAKONDA , DEIBITSUDO ESU KURISUTEII
Abstract: PURPOSE: To provide a processor executing operation by an operand with variable size. CONSTITUTION: The processor 10 contains an instruction decoder 18 that includes a means dividing an operand into fields in a variable size operand, a means designating whether or not each field is defined with respect to its operation, and contains a re-order buffer including an operand data storage memory coupled with the decoder 18, a means detecting data dependency to each operand filed independently of other field, buses 30, 31, 32 coupled with the buffer 26 and communicating operand data for a field defined independently of other field, and function units 20, 21, 22, 80 coupled with the buses, executing the operation and generating execution result data.
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公开(公告)号:JPH07334361A
公开(公告)日:1995-12-22
申请号:JP13401195
申请日:1995-05-31
Applicant: ADVANCED MICRO DEVICES INC
Abstract: PURPOSE: To speedily and efficiently generate and execution program counter value by using a low-order program counter value bit from a fetch program counter circuit in an execution program counter circuit. CONSTITUTION: The execution program counter generation circuit 598 is provided with a low-order program counter generator 600, a high-order program counter generator 602 and an execution program counter controller 604. The low-order program counter generator 600 has an entry multiplexer 610, a branch multiplexer 612 and a register 614. The entry multiplexer 610 receivers the part of the lower four bits of a program counter value of an instruction and gives one of the counter values to the branch multiplexer 612. The branch multiplexer 612 receives the branched low-order bits, gives four bits low-order execution counter value to the register 614 and outputs the value as the next execution program counter value.
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