公开(公告)号：JPH07295811A

公开(公告)日：1995-11-10

申请号：JP10142795

申请日：1995-04-25

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIERARUDO DEI ZURAASUKI JIYUNI ,  SUKOTSUTO EI HOWAITO ,  MIYURARI ESU CHINNAKONDA ,  DEIBITSUDO ESU KURISUTEII

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

Abstract: PURPOSE: To provide a processor executing operation by an operand with variable size. CONSTITUTION: The processor 10 contains an instruction decoder 18 that includes a means dividing an operand into fields in a variable size operand, a means designating whether or not each field is defined with respect to its operation, and contains a re-order buffer including an operand data storage memory coupled with the decoder 18, a means detecting data dependency to each operand filed independently of other field, buses 30, 31, 32 coupled with the buffer 26 and communicating operand data for a field defined independently of other field, and function units 20, 21, 22, 80 coupled with the buses, executing the operation and generating execution result data.