公开(公告)号：JPH05314062A

公开(公告)日：1993-11-26

申请号：JP21731791

申请日：1991-08-28

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DAGURASU GEFUAATO ,  JIEIMUZU MAKUDONARUDO ,  GOBINDA KAMASU

IPC: G06F13/36 ,  G06F13/40 ,  G06F15/78 ,  H01L21/822 ,  H01L27/04

Abstract: PURPOSE: To provide a digital processor which is constituted as an integrated circuit on a single substrate for housing a plurality of peripheral buses. CONSTITUTION: A device 10 positioned on a single substrate 12 contains a computer processor 14, a connection 16 for S-bus, and a supporting peripheral device 18 incorporated with an S-bus interface circuit 20, and a bus master supporting circuit 22. A connection 24 for M-bus is related to a dynamic random access memory (RAM) controller 28, a random access memory (RAM), an M-bus supporting peripheral device 26 containing a controller 30. An S-bus supporting peripheral device 34 is correlated with an X-bus connection 32 and contains an X-bus interface 36.

公开(公告)号：JPH04332063A

公开(公告)日：1992-11-19

申请号：JP21828391

申请日：1991-08-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DAGURASU GEFUAATO ,  JIEIMUZU MAKUDONARUDO

IPC: G06F13/36 ,  G06F13/14 ,  G06F13/40

Abstract: PURPOSE: To provide an economical device for control over access to a system bus by composing a bus master circuit, which connects a data bus outside a host computer to an internal bus in terms of operation, of a control and state device, etc. CONSTITUTION: The address page output signal 236 from a page address 230 of a bus master support circuit 22 is inputted to a memory hit comparison device 240 and an I/O hit comparison device 244. Further, address information 246 regarding memory operation is inputted to the memory hit comparison device 240 and address information 248 regarding input/output operation is inputted to the I/O hit comparison device 244. A control register 260 sets input/ output type or memory type operation. A local computer processor state is supplied to a hit detecting circuit 254. The hit detecting device 254, control register 260, and control and state device 29 outputs a signal 296, etc., controlling the hot internal bus.

公开(公告)号：JPH04245349A

公开(公告)日：1992-09-01

申请号：JP21981691

申请日：1991-08-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEIMUZU MAKUDONARUDO

IPC: G06F12/02 ,  G06F12/06 ,  G11C11/401

Abstract: PURPOSE: To improve the efficiency of a memory access procedure and memory access time in a memory controller to be used for memory system integrating plural memory banks. CONSTITUTION: The memory controller generates row and column addresses and address strobe signals and indicates whether a memory address is valid or not, which memory bank is addressed, the type of an addressed memory bank, and whether memory bank interleaving is possible or not in response to an intermediate memory address applied by a memory bank comparator 24 and a control signal. The memory controller includes row and column address allocators and applies row and column addresses in response to the intermediate memory address and the comparator 24. A memory bank selector applies row and column address strobe signals to a suitable memory bank in response to the intermediate memory address and the comparator 24.

公开(公告)号：JPH04245348A

公开(公告)日：1992-09-01

申请号：JP21981591

申请日：1991-08-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEIMUZU MAKUDONARUDO

IPC: G06F12/02 ,  G06F12/06 ,  G11C11/401

Abstract: PURPOSE: To allow a memory bank comparator to be used in a memory system including plural memory banks to determine whether a memory address is valid or not, which memory bank is addressed, the type of an addressed memory bank, and whether memory band interleaving is possible or not in response to each memory address in each cycle. CONSTITUTION: The memory bank comparator system includes a factor allocator 14 for allocating a factor to each memory bank correspondingly to the maximum number of storing positions in each bank, an adder 16 for summing factors and applying a sum corresponding to the sum of the maximum number of storing positions in a certain memory bank and the maximum number of storing positions of its preceding memory bank to the memory bank concerned and an address comparator 24 for applying an output indicating which memory bank is addressed by comparing a memory address with each sum.