-
公开(公告)号：JPH04332063A
公开(公告)日：1992-11-19
申请号：JP21828391
申请日：1991-08-29
Applicant: ADVANCED MICRO DEVICES INC
Inventor： DAGURASU GEFUAATO , JIEIMUZU MAKUDONARUDO
Abstract: PURPOSE: To provide an economical device for control over access to a system bus by composing a bus master circuit, which connects a data bus outside a host computer to an internal bus in terms of operation, of a control and state device, etc. CONSTITUTION: The address page output signal 236 from a page address 230 of a bus master support circuit 22 is inputted to a memory hit comparison device 240 and an I/O hit comparison device 244. Further, address information 246 regarding memory operation is inputted to the memory hit comparison device 240 and address information 248 regarding input/output operation is inputted to the I/O hit comparison device 244. A control register 260 sets input/ output type or memory type operation. A local computer processor state is supplied to a hit detecting circuit 254. The hit detecting device 254, control register 260, and control and state device 29 outputs a signal 296, etc., controlling the hot internal bus.
-
2.发明专利
公开(公告)号：JPH06314256A
公开(公告)日：1994-11-08
申请号：JP21733391
申请日：1991-08-28
Applicant: ADVANCED MICRO DEVICES INC
Inventor： DAGURASU GEFUAATO
Abstract: PURPOSE: To provide a system for executing communication between the plural peripheral equipments to which the operation parameters of the peripheral equipments are stored and a computer. CONSTITUTION: A computer processor 14 is operationally connected to a bus controller 90 and operational connection contains a CPU bus address bus 102, a CPU data bus 104 and CPU control and a state bus 106. The bus controller 90 is operationally connected to plural peripheral modules 108, 110 and 112 through plural external buses 114. The external buses 114 exist outside a substrate 12 where CPU 14 and the bus controller 90 are positioned. The external buses 114 contain an external address bus 116, an external data bus 118, an external control bus 120 and an external feedback bus 122. The peripheral modules 108, 110 and 112 are operationally connected to the external buses 114 by a branch bus. The feedback generation circuit of respective peripheral modules contains operation information against the respective peripheral equipments.
-
Patent Agency Ranking
公开(公告)号：JPH05314062A
公开(公告)日：1993-11-26
申请号：JP21731791
申请日：1991-08-28
Applicant: ADVANCED MICRO DEVICES INC
Inventor： DAGURASU GEFUAATO , JIEIMUZU MAKUDONARUDO , GOBINDA KAMASU
IPC: G06F13/36 , G06F13/40 , G06F15/78 , H01L21/822 , H01L27/04
Abstract: PURPOSE: To provide a digital processor which is constituted as an integrated circuit on a single substrate for housing a plurality of peripheral buses. CONSTITUTION: A device 10 positioned on a single substrate 12 contains a computer processor 14, a connection 16 for S-bus, and a supporting peripheral device 18 incorporated with an S-bus interface circuit 20, and a bus master supporting circuit 22. A connection 24 for M-bus is related to a dynamic random access memory (RAM) controller 28, a random access memory (RAM), an M-bus supporting peripheral device 26 containing a controller 30. An S-bus supporting peripheral device 34 is correlated with an X-bus connection 32 and contains an X-bus interface 36.
-
公开(公告)号：JPH04340644A
公开(公告)日：1992-11-27
申请号：JP21828491
申请日：1991-08-29
Applicant: ADVANCED MICRO DEVICES INC
Inventor： DAGURASU GEFUAATO , PEGII ABAROSU
IPC: G06F1/04 , G06F13/36 , G11C11/406
Abstract: PURPOSE: To facilitate the continuous execution of a specified function by generating an affirmative response signal in response to the existence of first input when a computing device is not in an operational interruption state. CONSTITUTION: An AND gate 114 generates a CPU holding signal with output 128 and sequentially impresses it on the input 130 of a computer processor 14. When the computer processor 14 is in an operation state, a CPU holding affirmative response signal with output 132. A clock synchronization circuit 116 impresses a system holding request signal which is clock-synchronized with output 134 and impresses it on input B of a multiplexer 118. When a CPU clock is turned on and when a DISABLE signal is not impressed with the input 136 of the multiplexer 118 or with the input 126 of the AND gate 114, the CPU holding affirmative response signal generated by the computer processor 14 is generated as a system holding affirmative response signal with the output 138 of an artificial holding affirmative response device 110.
-
公开(公告)号：JPH0855038A
公开(公告)日：1996-02-27
申请号：JP13189995
申请日：1995-05-30
Applicant: ADVANCED MICRO DEVICES INC
Abstract: PURPOSE: To integrate system management interruption and to give the priority of interruption by providing a central interruption control unit receiving interruption signals from plural I/O devices and dispersing them to designated processing units. CONSTITUTION: A system 200 contains the plural processing units 202-1 to 202-m connected to a main memory 204 through a CPU local bus 206. A bus bridge 208 connects a CPU local bus 2O7 to an I/O bus 210. Plural I/O peripheral equipments 212-1 to 212-n are connected to the I/O bus 210. Additional I/O device 214 and an interruption controller 216 are also connected to the I/O bus 210, The central interruption control unit 220 manages interruption received from the I/O devices 212-1 to 212-n and the interruption controller 216, disperses interruption among the processing units 202-1 to 202-m and manages inter- processor interruption and software interruption, which are generated by the processing units 202-1 to 202-m.
-
公开(公告)号：JPH06259373A
公开(公告)日：1994-09-16
申请号：JP21968591
申请日：1991-08-30
Applicant: ADVANCED MICRO DEVICES INC
Inventor： DAGURASU GEFUAATO
Abstract: PURPOSE: To provide a device used with a calculating device for controlling communication with plural peripheral equipments which applies plural different controller circuits for housing plural different operational modes for communication. CONSTITUTION: A single substrate device 10 includes a computer processor 14, connection 16 with an S-bus, and supporting peripheral equipment 18 including an S-bus interface circuit 20 and a bus master supporting circuit 22. Connection 24 with an M-bus is operated by an M-bus supporting peripheral equipment 26 including a DRAM controller 28 and a shadow random access memory controller 30, and connection 32 with an X-bus is operated by an X-bus supporting peripheral equipment 34 including an X-bus interface 36. The S-bus is used as an extended bus for an industrial standard signal generator, timing device, extended card and sub-system, the M-bus is used for communication with a direct DRAM interface, and the X-bus is used for an ROM, keyboard controller, and digit coprocessor.
-
7.发明专利
公开(公告)号：JPH04332067A
公开(公告)日：1992-11-19
申请号：JP21823691
申请日：1991-08-29
Applicant: ADVANCED MICRO DEVICES INC
Inventor： DAGURASU GEFUAATO
Abstract: PURPOSE: To provide a system which controls a communication between the computer processor and plural peripheral devices which are operably connected to plural external buses. CONSTITUTION: The computer processor, 14 is operably connected to a buffer transceiver circuit 81 like an internal bus 80 which is connected to the buffer transceiver circuit 81 through a local bus 110 is connected to buffers 21, 29, and 37. The buffer 21 is connected to an S bus 118, the buffer 29 is connected to a DRAM controller, and the buffer 37 is connected to an X bus. An internal peripheral device 140 is also connected operably to the internal bus 80. Bus control 90 is operably connected to the bus 80. High-speed characteristics of one peripheral device 132 and one memory device 124 may be actualized with a maximum potential without any limitation of a characteristic speed shown by the capacitance of the S bus 118. A combination of route specifications for operable interconnection that operation performed by the system 10 requires is predetermined and stored in a memory 91.
-
-
-
-
-
-
Search Results
7
records
(took 0.024 seconds)
