公开(公告)号：JPH08249085A

公开(公告)日：1996-09-27

申请号：JP25101995

申请日：1995-09-28

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIYOSEFU EI BEIRII

IPC: G06F1/00 ,  G06F1/04 ,  G06F1/08 ,  G06F1/20

Abstract: PROBLEM TO BE SOLVED: To provide a clock control circuit for controlling the frequency of the clock signals of a microprocessor. SOLUTION: This clock control circuit 101 controls the frequency of timing signals supplied to a clock generator and distribution unit 106 and the unit 106 supplies internal clock signals to the CPU core 102 of the microprocessor. A heat sensor 134 is integrated with a semiconductor die and the output signals are supplied to main and auxiliary temperature indicator units 130 and 132. The indicator units 130 and 132 respectively assert main and auxiliary indicator signals when the temperature of the die exceeds a main threshold value level and an auxiliary threshold value level. The main and auxiliary indicator units 130 and 132 are respectively related with hysteresis characteristics for which the main and auxiliary indicator signals are not de-asserted when they are asserted once until the temperature of the die becomes lower than prescribed first and second hysteresis points.

公开(公告)号：JPH0850570A

公开(公告)日：1996-02-20

申请号：JP11948695

申请日：1995-05-18

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIYOSEFU EI BEIRII

IPC: G06F12/08 ,  G06F15/163

Abstract: PURPOSE: To provide an integrated processor containing a cache controller which traces a physical address course of the system memory that corresponds to each entry in the cache memory. CONSTITUTION: An address tag and a state logic circuit 130 contain state information which consists of dirty bits allocated to each double word in every line and valid bits allocated to every line. The dirty bit shows whether a double length word is dirty or clean and the valid bit shows whether a line is valid or invalid. A cache controller 108 contains a snoop writeback control circuit 134 which monitors a local bus 112 to decide whether a memory cycle is executed by an alternate bus master 122 of the local bus 112. Between the memory cycles, a comparator circuit 132 decides whether cache hit occurs or not.

公开(公告)号：JPH096679A

公开(公告)日：1997-01-10

申请号：JP14620295

申请日：1995-06-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIYOSEFU EI BEIRII ,  SUTEIIBU ERU BERUTO

IPC: G06F13/16 ,  G06F12/08

Abstract: PURPOSE: To provide an integrated processor having higher performance and interchangeability with lower processors. CONSTITUTION: A cache controller 108 in a processor 101 includes a circuit 130 for grasping a physical address of a memory 114 which corresponds to each entry of a cache 106 and storing information indicating whether each cache line is valid or dirty, a circuit 134 for judging whether a memory cycle is executed or not based upon the contents of a substitutive bus master 122 and a circuit 132 for judging whether a cache hit is generated in the cycle or not. When a write cycle is generated by the bus master 122 and a cache hit is generated, data are outputted from the cache 106 if a corresponding line is dirty. When a read cycle is generated and hit, data are written in both the memory 114 and cache 106 and the dirty information of the cache 106 is updated as necessity.