公开(公告)号：JPH096679A

公开(公告)日：1997-01-10

申请号：JP14620295

申请日：1995-06-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIYOSEFU EI BEIRII ,  SUTEIIBU ERU BERUTO

IPC: G06F13/16 ,  G06F12/08

Abstract: PURPOSE: To provide an integrated processor having higher performance and interchangeability with lower processors. CONSTITUTION: A cache controller 108 in a processor 101 includes a circuit 130 for grasping a physical address of a memory 114 which corresponds to each entry of a cache 106 and storing information indicating whether each cache line is valid or dirty, a circuit 134 for judging whether a memory cycle is executed or not based upon the contents of a substitutive bus master 122 and a circuit 132 for judging whether a cache hit is generated in the cycle or not. When a write cycle is generated by the bus master 122 and a cache hit is generated, data are outputted from the cache 106 if a corresponding line is dirty. When a read cycle is generated and hit, data are written in both the memory 114 and cache 106 and the dirty information of the cache 106 is updated as necessity.