公开(公告)号：JPH04219021A

公开(公告)日：1992-08-10

申请号：JP4201291

申请日：1991-03-07

Applicant: ADVANCED MICRO DEVICES INC

Inventor： OMU PII AGURAWARU ,  JIYOOJI EICHI RANDAASU ,  NIKORASU EI SHIYUMIITSU ,  JIERII DEII MENSHIYU ,  KERII EI IRUGENSUTAIN

IPC: H01L21/82 ,  H03K19/177

Abstract: PURPOSE: To provide a programmable logic device with high speed performance by providing plural programmable logic blocks and a means of mutually connecting those logic blocks. CONSTITUTION: This circuit is provided with the same programmable logic circuits (blocks) mutually connected by a switch matrix. For example, four same programmable logic blocks 106A to 106D included in a single integrated circuit are mutually connected by a switch matrix 101 and are composed so as to be selectively connected to and disconnected from input and output pins. This divided logic structure can maintain larger functionally than conventional technology and on the other hand obtain high speed performance.

公开(公告)号：JPH06188724A

公开(公告)日：1994-07-08

申请号：JP18816393

申请日：1993-07-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： OMU PII AGURAWARU ,  KERII EI IRUGENSUTAIN

IPC: H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To provide a PLD(programmable logical device) cell used for the constitution of high density and high performance which simultaneously supports both synchronous and asynchronous operations. CONSTITUTION: A PLD cell includes two types of cells of PLB(programmable logical block) 201A, an I/O cell, an input macro cell 206A and the sub-banks of programmable output and input switch matrix banks. Every cell of PLB includes many product terms. One or more product terms of a cluster are programmably available to the cluster. When the product terms are separated from the cluster, they are used for the polarity control or an asynchronous function of the output signal of a logical macro cell. When the product terms are connected to the cluster, the cells of the PLB are used for the synchronous operations but each product term is related to the logical macro cell. Thereby, the logical macro cell is individually constructed for an asynchronous operation by merely separating a proper product term from its cluster and also using the product term to a desired asynchronous function.

公开(公告)号：JPH06188723A

公开(公告)日：1994-07-08

申请号：JP18530993

申请日：1993-07-27

Applicant: ADVANCED MICRO DEVICES INC

Inventor： OMU PII AGURAWARU ,  JIERII DEI MOENCHI ,  KERII EI IRUGENSUTAIN

IPC: H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To provide an architecture used for a programmable logical device which can reduce proportionally from low density to very high density. CONSTITUTION: The >=2 programmable logical blocks 210A, 215A and BC are connected to each other by a switch matrix including a programmable input switch matrix 220A and a programmable concentrated switch matrix 230. Then the programmable logical blocks receive the input signals only from the concentrated switch matrix 230. Output signals sent from the programmable logical blocks are connected to plural I/O pins 205A by an output switch matrix 240A and also sent directly to the input switch matrix 220A. Furthermore, an input macro cell 203A connects the signals existing on the I/O pin that drives the input macro cell, i.e. on the related I/O pins to the programmable input switch matrix 230.