COMPUTER SYSTEM AND METHOD FOR ACTIVATION AND INACTIVATION OF CLOCK-RUN CHARACTERISTIC FOR PERIPHERAL BUS

    公开(公告)号:JPH08194663A

    公开(公告)日:1996-07-30

    申请号:JP23134895

    申请日:1995-09-08

    Abstract: PROBLEM TO BE SOLVED: To provide a system for automatically judging whether or not clock run characteristics for saving power can be supported and performing activation or inactivation. SOLUTION: This system 100 is provided with a bus interface and arbiter unit 106 and it is provided with a clock control circuit 120 for turning ON/OFF a clock generator 122 for generating bus clock control signals and status and command registers 142 and 144. The system 100 is further provided with a peripheral bus master and a slave device 108 and 118 and they are respectively provided with the status and command registers 242 and 244 as well. The respective status and command registers are respectively provided with exclusive bits for providing information relating to whether or not the clock run characteristics can be supported inside the system.

    ELECTRIC-POWER CONTROL UNIT FOR COMPUTER SYSTEM AND METHOD FOR CONTROL OF ELECTRIC POWER AT INSIDE OF COMPUTER SYSTEM

    公开(公告)号:JPH07302133A

    公开(公告)日:1995-11-14

    申请号:JP1226295

    申请日:1995-01-30

    Abstract: PURPOSE: To provide a power management system optimizing the power management in a computer system using an integrated processor. CONSTITUTION: When the computer system is reset, the power management unit 208 enters a ready state at which a CPU clock signal and a system clock signal are driven at the maximum frequency. When a primary activity is not detected within a time, the power management unit transits from the ready state, to a pause state where a frequency of the CPU clock signal is reduced, a standby state where the CPU clock signal is stopped, and a holding state where both the CPU clock signal and the system clock signal are stopped and power supply to selected circuit sections is stopped continuously. When a secondary activity is detected in the pause state or the ready state, the power management unit enters a transient state where both the CPU clock signal and the system clock signal are driven at a maximum frequency for a predetermined time.

    ELECTRIC POWER CONTROL SYSTEM FOR COMPUTER SYSTEM

    公开(公告)号:JPH0836445A

    公开(公告)日:1996-02-06

    申请号:JP1226195

    申请日:1995-01-30

    Abstract: PURPOSE: To provide a power managing unit in which the power consumption amounts of the overall system can be minimized, even when malfunctioning software is loaded in a computer system. CONSTITUTION: A power control unit 122 and a clock control unit 124 are respectively constituted, dependent on the state of a power managing unit 120, so that a power can be applied or removed to or from a certain specific component in a computer system, and the frequencies of both a CPU clock signal and a system clock signal can be increased or decreased. The power managing unit 120 includes a software constitution enabling state register 136 for allowing system softward, such as software for an advanced power management(APM) in a system BIOS to control the state of the power managing unit. Therefore, the AMP software is applied for controlling the state of the power managing unit.

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