公开(公告)号：JPH08180013A

公开(公告)日：1996-07-12

申请号：JP23382795

申请日：1995-09-12

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SHIYAAMAN RII ,  MAIKERU TEII WAIZAA

IPC: G06F13/36 ,  G06F1/08 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To provide a system for promoting the operation at a higher clock frequency of a peripheral bus such as a PCI bus. SOLUTION: An enable line (66MHzENABLE) is connected to respective devices 70 and 80 present on the PCI bus 100. When all the devices can perform a high frequency operation (66MHz, for instance,) the enable line is pulled up through a pull-up register 62. For the device incapable of the high frequency operation, at the time of corresponding to specifications in an industrial field at present, the enable line is connected to the ground in the inside. Thus, the enable line is asserted in the case that all the PCI devices 70 and 80 support the high frequency operation but it is de-asserted otherwise. An exclusive state bit for making the system alarm non-matching between the device and bus ability can be provided and a configuration register can be automatically reconstituted when the parameter of the system is changed.

公开(公告)号：JPH01231159A

公开(公告)日：1989-09-14

申请号：JP31604788

申请日：1988-12-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： UIRIAMU MAIKURU JIYONSON ,  TEIMOSHII ARAN ORUSON ,  DORUU JIYON DATON ,  SHIYAAMAN RII ,  DEIBITSUDO UIRIAMU SUTAANAA

IPC: G06F13/28 ,  G06F13/36

Abstract: PURPOSE: To facilitate bus interconnection and transfer by providing four address-mapped input/output ports in data transfer between peripheral buses with low performance and a high performance channel interfaced with a CPU. CONSTITUTION: In a reduction instruction set computer (RISC) system, a data transfer controller 104 interconnecting a remote bus 120 being a high performance channel and a local bus 110 being a low performance channel is interconnected to an address bus 111 and a data bus 112. The data transfer controller 104 realizes four address-mapped input/output ports and the ports are expressed by local buses in a data memory address space or an input output address space. Since the port is address-mapped, address designation on the local bus is independent on address designation on a remote bus. The remote bus access is overlapped with a local bus access by advance read and post write for the ports.

公开(公告)号：JPH08194663A

公开(公告)日：1996-07-30

申请号：JP23134895

申请日：1995-09-08

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SHIYAAMAN RII ,  MAIKERU TEII WAIZAA

IPC: G06F13/36 ,  G06F1/32

Abstract: PROBLEM TO BE SOLVED: To provide a system for automatically judging whether or not clock run characteristics for saving power can be supported and performing activation or inactivation. SOLUTION: This system 100 is provided with a bus interface and arbiter unit 106 and it is provided with a clock control circuit 120 for turning ON/OFF a clock generator 122 for generating bus clock control signals and status and command registers 142 and 144. The system 100 is further provided with a peripheral bus master and a slave device 108 and 118 and they are respectively provided with the status and command registers 242 and 244 as well. The respective status and command registers are respectively provided with exclusive bits for providing information relating to whether or not the clock run characteristics can be supported inside the system.

公开(公告)号：JPH01205366A

公开(公告)日：1989-08-17

申请号：JP31604688

申请日：1988-12-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： UIRIAMU MAIKURU JIYONSON ,  TEIMOSHII ARAN ORUSON ,  DORUU JIYON DATON ,  SHIYAAMAN RII ,  DEIBITSUDO UIRIAMU SUTAANAA

IPC: G06F13/28 ,  G06F13/36

Abstract: PURPOSE: To contrive a bus mutual connection and data transfer by placing a direct memory access transfer channel from a 1st bus to a 2nd bus and a direct memory access transfer channel from the 2nd bus to the 1st bus in operation. CONSTITUTION: A DMA channel is a high-performance channel coupled with the CPU of a reduced instruction set computer RISC 101, namely, used to transfer data between a local bus 110 and a typically lowperformance remote bus 120. Then a data transfer unit 104 actualizes four address-mapped input/output ports on the bus 110. Those ports provide a gateway from the bus 110 to a bus 120, and consequently the RISC 101 fitted to the bus 110 can access devices and memories on the bus 120 directly. Consequently, the bus mutual connection and data transfer which exerts no large influence on the performance of the devices fitted to the bus are enabled.

公开(公告)号：JPH0870163A

公开(公告)日：1996-03-12

申请号：JP17723995

申请日：1995-07-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SHIYAAMAN RII ,  MAAKU MAA

IPC: H02J1/00 ,  H02J3/00 ,  H05K1/02

Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit board operable on a first and a second prescribed voltages. SOLUTION: A printed circuit board 100 includes metallic layers, one of which is split into two parts 104 and 106 which are electrically insulated from each other and substantially flush with each other, and the one part 106 is related to a first prescribed voltage. The other part 104 is related to a second prescribed voltage, and furthermore the board 100 contains first signal pins 105 connected to the electrically insulated part 106 and at least a capacitor 108, connected to the other part 106 insulated electrically from a grounding and the signal pins 105 is given an alternating current path.

公开(公告)号：JPH0258792A

公开(公告)日：1990-02-27

申请号：JP16247689

申请日：1989-06-23

Applicant: ADVANCED MICRO DEVICES INC

Inventor： PAASHII AARU ARAIA ,  SHIYAAMAN RII

IPC: G11C11/401 ,  G06F12/02 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C11/409 ,  G11C11/4096

Abstract: PURPOSE: To minimize memory access time by renewing a data position accessed presently and comparing it as necessary with the data accessed previously. CONSTITUTION: A first data is accessed at predetermined line and row positions. The predetermined row position for the first data is recorded in a row latch 106. A second data position is recorded in a row register 107. Then, the first and the second data positions, i.e., the contents of the row latch 106 is compared with those of the row register 107 by a row comparator 107a. If both row values of the first and the second data are the same, a row comparison signal RC is generated, changing only the line address in response to the row comparison signal RC. Thus, the access time is minimized.