公开(公告)号：JPH04340644A

公开(公告)日：1992-11-27

申请号：JP21828491

申请日：1991-08-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DAGURASU GEFUAATO ,  PEGII ABAROSU

IPC: G06F1/04 ,  G06F13/36 ,  G11C11/406

Abstract: PURPOSE: To facilitate the continuous execution of a specified function by generating an affirmative response signal in response to the existence of first input when a computing device is not in an operational interruption state. CONSTITUTION: An AND gate 114 generates a CPU holding signal with output 128 and sequentially impresses it on the input 130 of a computer processor 14. When the computer processor 14 is in an operation state, a CPU holding affirmative response signal with output 132. A clock synchronization circuit 116 impresses a system holding request signal which is clock-synchronized with output 134 and impresses it on input B of a multiplexer 118. When a CPU clock is turned on and when a DISABLE signal is not impressed with the input 136 of the multiplexer 118 or with the input 126 of the AND gate 114, the CPU holding affirmative response signal generated by the computer processor 14 is generated as a system holding affirmative response signal with the output 138 of an artificial holding affirmative response device 110.