公开(公告)号：JPH09186154A

公开(公告)日：1997-07-15

申请号：JP20211996

申请日：1996-07-31

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SHINYA AASAA WAN ,  MOHAMEDO BII BANDARI ,  SHIYAMU GAAGU ,  BURUUSU PITSUKERUSAIMAA

IPC: H01L21/31 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/29 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing the top-side structure of a semiconductor device. SOLUTION: A thin layer 40 of oxynitride is formed on a device. A patterned metal layer and a SOG(Spin On Glass) layer 42 for flattening are formed on the thin oxynitride layer 40, and then the thin portions of the SOG layer 42 is removed by etching to expose parts of the thin oxynitride layer 40. A thick oxynitride layer 44 is formed so that it will be firmly combined with the thin oxynitride layer. Thereafter, a thin nitride layer permeable to ultraviolet rays may be added to thus obtained structure prior to the application of plastic package material.

公开(公告)号：JPH03173480A

公开(公告)日：1991-07-26

申请号：JP34115890

申请日：1990-11-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SHINYA AASAA WAN

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To improve adhesion of a multilayer control gate to a polycrystalline Si layer, located below a silicide layer, by forming a multilayer control gate including a heavily doped polycrystalline Si layer adjacent to a gate oxide layer on a substrate. CONSTITUTION: A gate oxide is formed on a Si substrate 10, a layer (polycrystalline Si layer) 14 for material of a floating gate is provided on it, and P is doped by annealing it in an atmosphere including POCl3 . An oxide layer 16 between gates, a polycrystalline Si layer 18, a silicide layer (TaSi2 , WSi2 , and other layers) 20, a polycrystalline Si layer 22, and a cap formation oxide layer 24 are successively formed on it, layers 18-24 are etched for forming a pattern, and a control gate line 26 is formed. The layers 16 and 14 are etched with the line 26 as a mask, a floating gate 114 is formed, and a gate structure 28 is completed. After ions are implanted with the gate 28 as a mask for forming drain regions 36 and 38, a thick oxide is grown at the side of the gate structure 28, and a metallization layer and a passivation layer are provided, thus forming an FET.