公开(公告)号：JPH06252717A

公开(公告)日：1994-09-09

申请号：JP863794

申请日：1994-01-28

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUTEFUAN SHII HOON ,  SUKOTSUTO EICHI AARU MATSUKUMA

IPC: H03K5/151 ,  G06F1/04 ,  H03K5/156 ,  H03K5/15

Abstract: PURPOSE: To provide a digital clock waveform generator for generating an inside clock signal having high or low frequencies which is the same as a clock signal applied from the outside by on-chip and a method for generating the clock signal for a microprocessor or another digital circuit. CONSTITUTION: A waveform generator includes delay chains 40A-D and a controller 70 for making the propagation delay of the delay chains 40A-D coincident with the cycle of an input timing signal. A waveform generator exactly controls the duty cycle of an inside generated clock signal, and quickly starts and stops the inside clock signal for power reduction. The waveform generator can be applied a system clock, and include a circuit for exactly controlling a phase relation between the dock signals. The waveform generator can be easily manufactured by a digital circuit for automatically compensating a changing environment condition such as an operating voltage or temperature.

公开(公告)号：JPH06230849A

公开(公告)日：1994-08-19

申请号：JP33222593

申请日：1993-12-27

Applicant: ADVANCED MICRO DEVICES INC

Inventor： GOPI GANAPASHII ,  SUTEFUAN SHII HOON

IPC: G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  H03K5/15

Abstract: PURPOSE: To provide a distributed clock generation mechanism for a microprocessor which reduces the electromagnetic disturbance noises and power consumption. CONSTITUTION: Plural smaller clock generator circuits 16 to 18 are distributed on a die instead of a single and large internal clock generator circuit which meets necessary driving conditions of the rest of circuit constitution of a microprocessor die, and each of generator circuits 16 to 18 generates clock signals to drive different parts of the microprocessor circuit constitution, undergoes the mutual load matching to minimize the skews among the clock signals and receives the synchronized timing signals from a master timing distribution circuit 14. This mechanism adjusts both speed and volume of current which is charged and discharged at a prescribed position of a semiconductor die and therefore reduces electromagnetic disturbance noises and also increases the SN ratio. Electromagnetic disturbance noises and power consumption are reduced by decreasing the load which is applied on the distributed clock generators through the internal transfer routes of clock signals.

公开(公告)号：JPH07326949A

公开(公告)日：1995-12-12

申请号：JP854194

申请日：1994-01-28

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUTEFUAN SHII HOON

IPC: G06F1/04 ,  G11C11/407 ,  H03K5/13 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

Abstract: PURPOSE: To dynamically adapt the butter circuit to operation conditions and manufacturing parameters by connecting the control terminal of a buffer unit to a speed detector unit and changing the driving force of the buffer unit in response to a control signal. CONSTITUTION: The self-adjustment driving force variable buffer circuit is provided with the speed detector unit 10 for monitoring the relative speed of an integrated circuit and the buffer unit 12 connected between an input signal IN and an output signal OUT. The unit 10 measures the speed of the integrated circuit in regard to the period of an input lock signal INCLK and generates a control signal indicating a circuit speed vector. The unit 12 receives the circuit speed vector and applies related driving force depending on the vector in response to the vector. The vector is changed in response to the dispersion of parameters such as a manufacturing process, operation frequency, operation voltage, and operation temperature. Thereby the driving force of the buffer circuit is adjusted in accordance with a circuit speed.

公开(公告)号：JPH06303124A

公开(公告)日：1994-10-28

申请号：JP694694

申请日：1994-01-26

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUKOTSUTO EICHI AARU MATSUKUMA ,  JIEIMUZU MAIKERU BUKIYANAN ,  SUTEFUAN SHII HOON

IPC: H03K17/12 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

Abstract: PURPOSE: To improve the flexibility on production and to reduce the cost by obtaining a version of a driving force which is different dependently upon whether a bonding wire is connected to an integrated circuit package or not. CONSTITUTION: When a variable clock signal driver 10 is used in environments of a high performance and a relatively high frequency, a low driver logic unit 12 and a high driver logic unit 14 are enabled to drive transistor TR output stages 26 and 28. This is achieved by connecting an optional bonding wire 31 between a bonding pad 30 and a ground pin 51A of a package 50. When the driver 10 is used in environments of a lower frequency, the bonding pad 30 is in the floating state. A package grounding sense circuit 20 disables the unit 14 in response to it. Consequently, the output stage 28 reduces a maximum operation frequency. Thus, an inexpensive packaging technique can be used.