公开(公告)号：JPH06282453A

公开(公告)日：1994-10-07

申请号：JP29034193

申请日：1993-11-19

Applicant: ADVANCED MICRO DEVICES INC

Inventor： GOPI GANAPASHII ,  TSUAN TORAN

IPC: G06F11/22 ,  G11C29/36 ,  G11C29/40 ,  G11C29/44

Abstract: PURPOSE: To provide the mechanism and method for testing a known error place in an embedded array with a series of predetermined test patterns. CONSTITUTION: The said mechanism includes a determinative test pattern generator 14 which sends a test pattern to the array 12. The pattern is previously selected according to the fault trend of the array 12. The contents of the array 12 are read out and compared with the test pattern to generate a current error term. The current error term is compressed by a register 16 through logical operation and it saves an error display. The contents of the register 12 constitute a cumulative error term and can be read out to judge whether an error occurs or not. Respective columns of the tested array 12 correspond to bit positions in the cumulative error term and a user can judge which column in the array 12 causes the error.

公开(公告)号：JPH0715291A

公开(公告)日：1995-01-17

申请号：JP233194

申请日：1994-01-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TAN TORAN ,  GOPI GANAPASHII ,  MAIKERU DEI GOTSUDAADO ,  ROBAATO SATSUDEN

IPC: H03K3/356 ,  G06F13/40

Abstract: PURPOSE: To remove precharge rippling, and to remove a noise by providing a latch circuit for delaying the latching of data from a bus to a receiving circuit. CONSTITUTION: Data from a pre-charged data bus are transmitted to a data line 4, and the input of a latch 20 is connected with the data line 4, and the output of the latch 20 is connected with the receiving circuit of an asynchronizing circuit 22. The gate of the latch 20 is connected with the output of a structure for activating latch, and a pre-charge value is not transmitted from the pre-charged bus to the asynchronizing circuit 22. The activating structure includes an AND gate 32, and this is provided with input lines 34 and 36 and an output. At that time, inverted DATA VALID signal and DATA CLOCK signal are received by the AND gate 32, and the output is turned into an H level only when the pre-charged bus is operated with a data drive phase, and the data are driven by the precharged bus. Therefore, the latch 20 is not activated until the data are driven by the precharged bus.

公开(公告)号：JPH08254571A

公开(公告)日：1996-10-01

申请号：JP26684995

申请日：1995-10-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BURAIAN DEI MATSUKUMIN ,  GOPI GANAPASHII

IPC: G01R31/28 ,  G06F17/50 ,  H03K3/037 ,  H03K19/00

Abstract: PROBLEM TO BE SOLVED: To make it possible to emulate a level detecting latch effectively by suing a high-frequency enabled signal, and clocking an edge detecting latch. SOLUTION: A level-detecting emulating circuit 20 has an edge detecting latch 22 and an AND gate 24. The gate 24 receives a system clock signal (PHI) and a high-frequency clock signal (HCLK) and imparts a high-frequency enabled clock signal (HEN) to the latch 22. The latch 22 is a DFF and feeds the signal, which is applied to the D input terminal, to the Q output terminal when a rising edge is fed to the input of the FF. Thus, the edged detecting latch 22 can emulate the level detecting latch. At this time, the frequency ratio of HCLK and PHI is made to be 10:1, and the errors caused by the too low ratio and the waste of the using time caused by the too high ratio are reduced.

公开(公告)号：JPH06230849A

公开(公告)日：1994-08-19

申请号：JP33222593

申请日：1993-12-27

Applicant: ADVANCED MICRO DEVICES INC

Inventor： GOPI GANAPASHII ,  SUTEFUAN SHII HOON

IPC: G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  H03K5/15

Abstract: PURPOSE: To provide a distributed clock generation mechanism for a microprocessor which reduces the electromagnetic disturbance noises and power consumption. CONSTITUTION: Plural smaller clock generator circuits 16 to 18 are distributed on a die instead of a single and large internal clock generator circuit which meets necessary driving conditions of the rest of circuit constitution of a microprocessor die, and each of generator circuits 16 to 18 generates clock signals to drive different parts of the microprocessor circuit constitution, undergoes the mutual load matching to minimize the skews among the clock signals and receives the synchronized timing signals from a master timing distribution circuit 14. This mechanism adjusts both speed and volume of current which is charged and discharged at a prescribed position of a semiconductor die and therefore reduces electromagnetic disturbance noises and also increases the SN ratio. Electromagnetic disturbance noises and power consumption are reduced by decreasing the load which is applied on the distributed clock generators through the internal transfer routes of clock signals.

公开(公告)号：JPH06230088A

公开(公告)日：1994-08-19

申请号：JP31006193

申请日：1993-12-10

Applicant: ADVANCED MICRO DEVICES INC

Inventor： GOPI GANAPASHII

IPC: G01R31/28 ,  G01R31/3185

Abstract: PURPOSE: To ensure the propagation by connecting the first and the second latch elements with the first latch output and the second data input and also with the first and the second shift mechanism having a shift input and a test clock input, and giving the data of the shift inputs to the first and second latch elements with the inputs of the first and second test clocks. CONSTITUTION: The data from a combination element 90 is given to the data inputs 104, 114, 124. A scan cell 100 corresponds to ϕ2 clock of an input 106 and stores the data of the input 104 in the inverted form, and this is passed through a data output 101 and then inverter 103 to undergo re-inversion to be fed to the data output 101. Scan cells 110, 120 operate approx. in the same manner wherein only the cell 120 corresponds to ϕ1 clock. In testing the part 92 of an IC 95, the data is taken in from data inputs 91, 94, 93 using the ϕ1 and ϕ2 clocks and loaded in the cells. Then the data is shifted through shift inputs 129, 119, 109 and shift outputs 128, 118, 108 and sent to external pins finally.

公开(公告)号：JPH08262104A

公开(公告)日：1996-10-11

申请号：JP26683695

申请日：1995-10-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： GOPI GANAPASHII ,  DEIBITSUDO BII UITSUTO

IPC: G01R31/28 ,  G01R31/3185 ,  G06F5/06 ,  G06F11/26 ,  G06F17/50 ,  H03K3/037

Abstract: PROBLEM TO BE SOLVED: To convert a multiple-phase circuit into a single clock-edge circuit by a constitution, wherein a single clock edge test system is used and the multiple-phase circuit is emulated. SOLUTION: For converting a multiple-phase circuit such as a circuit 500 into a single clock edge trigger circuit, the signal of an input multiplexer 506 is imparted into the input terminal of an edge inspection FF 502, and the signal of an output multiplexer 508 is imparted into the output terminal of the FF 502. When the enable signal EN on a control line 514 is activated and made to be data 1, the multiplexer 508 selects a signal A and transfers the signal into an output line 518. When the signal EN is deactivated and made to be data 0, the finally latched data values in the FF 502 become available by the edge of a system clock signal CLK. Even if the signal EN is deactivated and the adequate signal A cannot be utilized on the input line 51 in this way, the adequate data can be utilized by storing the data with the FF 502.

公开(公告)号：JPH07152451A

公开(公告)日：1995-06-16

申请号：JP19536294

申请日：1994-08-19

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUTEIIBUN SHII KUROMAA ,  GOPI GANAPASHII

IPC: G06F11/22 ,  G01R31/317 ,  G06F1/04 ,  G06F1/06

Abstract: PURPOSE: To provide a device for synchronizing a plurality of asynchronous circuits during a test operation. CONSTITUTION: The device is provided with first (26) and second (28) clock inputs, test mode input (30) and output (24). The device receives first clock signals from a first clock by the first clock input and receives second clock signals from a second clock by the second clock input. Corresponding to the state of test mode signals in the test mode input, the device generates the first clock signals or the second clock signals in the output. A first circuit is arranged so as to be driven by the output of the device, and in the meantime, a second circuit is driven by one of the first and second clocks. As a result, the first and second circuits are driven by the different clocks when the test mode signals are in one state and are driven by the same clock when the test mode signals are in the different state.

公开(公告)号：JPH06230848A

公开(公告)日：1994-08-19

申请号：JP33038393

申请日：1993-12-27

Applicant: ADVANCED MICRO DEVICES INC

Inventor： GOPI GANAPASHII

IPC: G06F1/04 ,  G06F1/06 ,  G06F1/08

Abstract: PURPOSE: To vary the speed of an internal microprocessor circuit in dependence on a register programmed by software by providing a timing signal source, a clock generator circuit generating internal clock signals, etc. CONSTITUTION: A timing signal source 12 sends a pair of timing signals to a master timing distribution circuit 14, and a clock selection circuit 13 has a clock speed switching function which makes a microprocessor 10 operable by means of the frequency that can be selected by a user. The distribution circuit 14 receives a pair of timing signals from the signal source 12 and sends master timing signals of designated frequency to distributed clock generator circuits 16 to 18 respectively in dependence on the clock selection signals sent from the selection circuit 13. The generator circuits 16 to 18 produce respectively a pair of clock signals having phase shifted by 180 deg. with each other and drive related circuit areas 20 to 25 respectively.

公开(公告)号：JPH06213974A

公开(公告)日：1994-08-05

申请号：JP28643593

申请日：1993-11-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： GOPI GANAPASHII ,  ROBAATO SADEN ,  SUTEIIBU HOON

IPC: G01R31/28 ,  G01R31/3185

Abstract: PURPOSE: To facilitate the test of an IC using sequential elements by providing a drive scan latch inputting the data signal and test mode signal. CONSTITUTION: When a circuit portion 12 of an IC 10 containing sequential elements such as latches 14, 16, 18, 20 is to be tested, the test mode is started by the signal from the test mode input 57 of a drive scan latch 30, the latch 30 feeds the constant logical control signal to the input 31 of an AND gate 26, and the ϕ1 clock signal at the input 28 is fed to the latch 20 for the clock operation. Various elements of the circuit portion 12 feed various test data from inputs 32, 34, and the output values obtained from pins 38, 40, 42 are compared with the expected output values for testing. The ϕ1, ϕ2 clock signals are fed to the latches 14, 16, 18, 20 and test data are fed to the inputs 34 for testing, for example. When the latch 30 is used, the use of the scan latch for individual latches can be effectively avoided.