THRESHOLD VOLTAGE COMPACTING FOR NON-VOLATILE SEMICONDUCTOR MEMORY DESIGNS
    1.
    发明公开
    THRESHOLD VOLTAGE COMPACTING FOR NON-VOLATILE SEMICONDUCTOR MEMORY DESIGNS 有权
    压缩非易失性存储器的使用电压分布

    公开(公告)号:EP1386323A1

    公开(公告)日:2004-02-04

    申请号:EP02709575.1

    申请日:2002-02-19

    CPC classification number: G11C16/3409 G11C16/3404

    Abstract: A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design are disclosed. The threshold voltage is compacted by erasing (602) a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying (604) at least one fast-erase memory cell; selectively soft-programming (606) the memory cells; and erasing (608) subsequent to selectively soft-programming.

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