Abstract:
A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design are disclosed. The threshold voltage is compacted by erasing (602) a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying (604) at least one fast-erase memory cell; selectively soft-programming (606) the memory cells; and erasing (608) subsequent to selectively soft-programming.
Abstract:
A low power charge pump (300) is disclosed. A pump driving node (270) of a first pump stage is selectively coupled to a pump driving node (271) of the subsequent pump stage. Subsequent to a transfer of charge from a first pump stage to a subsequent stage, the first (270) and subsequent (271) pump driving nodes are coupled. Residual charge on a first stage pump driving node (270) is thereby transferred to a subsequent pump driving node (271). Subsequent to the transfer of charge from the first pump driving node (270) to the second pump driving node (271), the nodes are uncoupled. By selectively coupling a first pump stage to a pump driving node (271) of the subsequent pump stage, the first pump driving node (270) may pre-charge the subsequent pump driving node (271), thereby reducing the energy that must be provided by clock driving circuitry (700) to produce a positive-going transition of a driving clock. Advantageously, pre-charging energy is taken from the first stage, reducing the energy that was heretofore dissipated by clock driving circuitry during a negative-going clock signal transition. In this novel manner conversion efficiency of a charge pump device may be beneficially increased, providing enhanced low power performance.
Abstract:
A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design are disclosed. The threshold voltage is compacted by erasing (602) a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying (604) at least one fast-erase memory cell; selectively soft-programming (606) the memory cells; and erasing (608) subsequent to selectively soft-programming.