公开(公告)号：WO1998008253A1

公开(公告)日：1998-02-26

申请号：PCT/US1997009424

申请日：1997-05-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I.

IPC: H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/823857

Abstract: A semiconductor manufacturing process for producing MOS integrated circuits having two gate oxide thicknesses. A first gate dielectric is formed on an upper surface of a semiconductor substrate. Thereafter, a masking layer is deposited on the first dielectric layer and patterned such that the first dielectric layer is exposed above a second region of the semiconductor substrate. The semiconductor wafer is then subjected to a thermal oxidation process such that a second gate dielectric is formed within the exposed second region of the semiconductor substrate. The second gate dielectric preferably has an oxide thickness that is unequal to the oxide thickness of the first gate dielectric layer. Thereafter, gate structures and source/drain structures are fabricated such that the integrated circuit includes a first transistor having a first gate dielectric thickness and a second transistor having a second gate dielectric thickness. In this manner, the integrated circuit can include selected transistors having a thinner gate dielectric for improving the performance of these selected transistors. In one embodiment, the n-channel transistors in a CMOS integrated circuit have a thinner gate oxide than the p-channel devices.

Abstract translation: 一种用于制造具有两个栅极氧化物厚度的MOS集成电路的半导体制造工艺。 第一栅极电介质形成在半导体衬底的上表面上。 此后，在第一电介质层上沉积掩模层并图案化，使得第一电介质层暴露在半导体衬底的第二区域之上。 然后对半导体晶片进行热氧化处理，使得第二栅极电介质形成在半导体衬底的暴露的第二区域内。 第二栅极电介质优选具有不等于第一栅极介电层的氧化物厚度的氧化物厚度。 此后，制造栅极结构和源极/漏极结构，使得集成电路包括具有第一栅极电介质厚度的第一晶体管和具有第二栅极电介质厚度的第二晶体管。 以这种方式，集成电路可以包括具有较薄栅极电介质的选择的晶体管，以改善这些选择的晶体管的性能。 在一个实施例中，CMOS集成电路中的n沟道晶体管具有比p沟道器件更薄的栅极氧化物。

公开(公告)号：WO1998003989A1

公开(公告)日：1998-01-29

申请号：PCT/US1997008728

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N. ,  FULFORD, H., Jim, Jr.

IPC: H01L21/336

CPC classification number: H01L29/66583 ,  H01L21/28123

Abstract: A semiconductor fabrication process for fabricating MOS transistors in which dielectric spacer structures are used prior to gate formation to reduce the gate length below the minimum feature size resolvable by the photolithography equipment. A semiconductor substrate having a channel region laterally disposed between a pair of source/drain regions is provided. A dielectric stack is formed on an upper surface of the semiconductor substrate and patterned to expose on upper surface of a spacer region of the semiconductor substrate. The spacer region includes the channel region and peripheral portions of the pair of source/drain regions proximal to the channel region. The patterning of the dielectric stack results in the formation of a pair of opposing sidewalls in the dielectric stack. Thereafter, a pair of first spacer structures are formed on the pair of opposing sidewalls such that the pair of first spacer structures cover or shadow the peripheral portions of the source/drain regions and such that an upper surface of the channel region is exposed. A gate structure is then formed on the upper surface of the channel region. The gate structure is laterally disposed between the pair of first spacer structures. A first dopant species is then introduced into the source/drain regions of the semiconductor substrate.

Abstract translation: 一种用于制造MOS晶体管的半导体制造工艺，其中在栅极形成之前使用电介质间隔物结构以将栅极长度减小到低于由光刻设备可分辨的最小特征尺寸。 提供了具有横向设置在一对源/漏区之间的沟道区的半导体衬底。 在半导体衬底的上表面上形成电介质堆叠并图案化以暴露在半导体衬底的间隔区域的上表面上。 间隔区域包括通道区域和靠近通道区域的一对源极/漏极区域的外围部分。 电介质堆叠的图案化导致在电介质叠层中形成一对相对的侧壁。 此后，在一对相对的侧壁上形成一对第一间隔结构，使得该对第一间隔结构覆盖或遮蔽源极/漏极区的周边部分，并使沟道区域的上表面露出。 然后在沟道区域的上表面上形成栅极结构。 栅极结构横向设置在一对第一间隔结构之间。 然后将第一掺杂剂物质引入到半导体衬底的源极/漏极区域中。

公开(公告)号：WO1998006137A1

公开(公告)日：1998-02-12

申请号：PCT/US1997013947

申请日：1997-08-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  FULFORD, H., Jim, Jr. ,  HAUSE, Fred, N.

IPC: H01L29/78

CPC classification number: H01L29/66537 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A selectively doped MOS transistor channel includes a deep impurity distribution and shallow impurity distribution. The deep impurity distribution is formed within high energy implant with an impurity of conductivity type opposite to the conductivity type of the source/drain regions of the transistor. In the n-channel regions, the deep impurity distribution preferably includes boron ions. The deep impurity distribution acts as a channel stop such that adjacent source/drain regions of the like type transistors are not inadvertently coupled during circuit operation. The shallow impurity distribution acts as a threshold implant by precisely controlling the doping of the transistor channel in the vicinity of the silicon oxide interface. The peak concentration of the shallow impurity distribution is located at a depth below the silicon surface which is greater than a depth typically associated with a thresold adjust implant. Because the impurity concentration of the shallow impurity distribution drops off rapidly from the peak concentration value, the concentration at the upper surface of the silicon substrate is not significantly greater than the doping of the silicon substrate itself. The light doping in the channel region of the transistor results in a substantially reduced threshold voltage for the transistor. Preferably, the threshold voltage of both the n-channel and p-channel devices has an absolute value of approximately 250 Mv. The lower threshold voltage translates into a higher IDsat when the transistor is operated under normal conditions (e.g., VGs = 3 volts, VDs = 3 volts, and VSb = 0 volts.)

Abstract translation: 选择掺杂的MOS晶体管沟道包括深杂质分布和浅杂质分布。 深度杂质分布形成在高能量注入内，杂质的导电类型与晶体管的源/漏区的导电类型相反。 在n沟道区域中，深杂质分布优选包括硼离子。 深杂质分布充当通道停止，使得相似型晶体管的相邻源极/漏极区在电路操作期间不会偶然耦合。 通过精确地控制在氧化硅界面附近的晶体管沟道的掺杂，浅杂质分布充当阈值注入。 浅杂质分布的峰值浓度位于硅表面以下的深度，其大于通常与thresold调整植入物相关的深度。 由于浅杂质分布的杂质浓度从峰值浓度值迅速下降，硅衬底上表面的浓度不会明显大于硅衬底本身的掺杂。 在晶体管的沟道区域中的轻掺杂导致晶体管的阈值电压显着降低。 优选地，n沟道和p沟道器件的阈值电压具有约250Mv的绝对值。 当晶体管在正常条件下操作时（例如，VGs = 3V，VDs = 3V，VSb = 0V），较低的阈值电压转换为较高的IDat。

公开(公告)号：WO1998002917A1

公开(公告)日：1998-01-22

申请号：PCT/US1997004991

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim

IPC: H01L21/336

CPC classification number: H01L29/66659 ,  H01L21/0338 ,  H01L21/28123 ,  H01L29/7835

Abstract: The method for fabrication of a non-symmetrical IGFET of the present invention includes providing a semiconductor substrate having an insulating film and a gate material. A first portion of the gate material overlying a first region of the semiconductor substrate is removed forming a first sidewall of a gate electrode. A dopant is implanted into the first region after forming the first sidewall. After the first region is implanted, a second portion of the gate material overlying a second region of the semiconductor substrate is then removed forming a second sidewall of the gate electrode. A dopant is implanted into the second region after forming the second sidewall. Spacers are formed adjacent to each of the sidewalls of the gate electrode. Then, a dopant is implanted into portions of the first and second regions of the semiconductor substrate outside the gate electrode and the spacers. In one embodiment of the invention, the first region is a heavily doped source region and the second region is a lightly doped drain region. In another embodiment of the present invention the first region is a lightly doped drain region and the second region is a heavily doped source region. In both embodiments, a part of the lightly doped drain region is retained beneath a spacer.

Abstract translation: 本发明的非对称IGFET的制造方法包括提供具有绝缘膜和栅极材料的半导体衬底。 去除覆盖半导体衬底的第一区域的栅极材料的第一部分，形成栅电极的第一侧壁。 在形成第一侧壁之后，将掺杂剂注入第一区域。 在植入第一区域之后，然后移除覆盖半导体衬底的第二区域的栅极材料的第二部分，形成栅电极的第二侧壁。 在形成第二侧壁之后，将掺杂剂注入第二区域。 隔板与栅电极的每个侧壁相邻形成。 然后，将掺杂剂注入到半导体衬底的第一和第二区域的位于栅电极和间隔物外部的部分中。 在本发明的一个实施例中，第一区域是重掺杂的源极区域，而第二区域是轻掺杂的漏极区域。 在本发明的另一个实施例中，第一区域是轻掺杂漏极区域，第二区域是重掺杂源极区域。 在两个实施例中，轻掺杂漏极区的一部分保持在间隔物的下方。

公开(公告)号：WO1997049126A1

公开(公告)日：1997-12-24

申请号：PCT/US1997002491

申请日：1997-02-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N. ,  FULFORD, H., Jim, Jr.

IPC: H01L21/336

CPC classification number: H01L29/66583 ,  H01L29/66492 ,  H01L29/66613 ,  H01L29/7834 ,  H01L29/7836

Abstract: A method of fabricating a transistor. A dielectric layer is formed on an upper surface of a semiconductor substrate. A photoresist layer is then deposited on a dielectric layer and patterned with a photolithography exposure device to expose a region of the dielectric layer having a lateral dimension approximately equal to the minimum feature size resolvable by the photolithography exposure device. The exposed region of the dielectric layer is then removed to form a trench in the dielectric layer having opposed dielectric sidewalls and to expose a channel region of the semiconductor substrate having a lateral dimension approximately equal to the minimum feature size. First and second spacer structures are then formed on the respective dielectric sidewalls. The spacer structures shadow peripheral portions of the exposed channel region. A channel dielectric is then formed between the first and second spacer structures. An outer surface of the spacer structure is then removed to expose peripheral portions of the channel region. A first concentration of a first impurity is then introduced into the peripheral portions of the semiconductor substrate and the channel dielectric is thereafter removed. A gate dielectric is then formed on the semiconductor substrate and a conductive gate structure, such as polysilicon, is formed over the gate dielectric.

Abstract translation: 一种制造晶体管的方法。 在半导体衬底的上表面上形成介电层。 然后将光致抗蚀剂层沉积在电介质层上并用光刻曝光装置进行图案化，以暴露电介质层的区域，该区域的横向尺寸近似等于由光刻曝光装置可分辨的最小特征尺寸。 然后去除电介质层的暴露区域，以在具有相对的电介质侧壁的电介质层中形成沟槽，并暴露半导体衬底的沟道区域，其横向尺寸近似等于最小特征尺寸。 然后在相应的电介质侧壁上形成第一和第二间隔物结构。 间隔结构遮挡了暴露的通道区域的外围部分。 然后在第一和第二间隔结构之间形成沟道电介质。 然后移除间隔结构的外表面以暴露通道区域的外围部分。 然后将第一杂质的第一浓度引入半导体衬底的周边部分，然后除去沟道电介质。 然后在半导体衬底上形成栅极电介质，并且在栅极电介质上形成诸如多晶硅的导电栅极结构。

公开(公告)号：WO1997041593A1

公开(公告)日：1997-11-06

申请号：PCT/US1997003823

申请日：1997-03-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N. ,  CHANG, Kuang-Yeh

IPC: H01L21/32

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76213 ,  Y10S438/981

Abstract: A method of forming a self-aligned filed oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

Abstract translation: 在不使用氮化硅的情况下形成自对准氮化物隔离结构的方法。 该方法包括在半导体衬底的上表面上形成电介质。 半导体衬底的上表面包括相互横向相邻的有源区和隔离区。 在植入电介质的顶部上构图光致抗蚀剂层，以在有源区上暴露植入电介质的区域。 然后通过植入电介质将氮注入有源区。 氮优选以0.5至2.0％的近似原子浓度引入半导体衬底。 在将氮气注入到半导体衬底中之后，剥离光致抗蚀剂层并除去注入电介质。 然后将晶片热氧化，使得具有第一厚度的场氧化物在隔离区上生长，并且在有源区上生长具有第二厚度的薄氧化物。 半导体衬底内的氮的存在阻碍了有源区中硅的氧化速率，使得薄氧化物的厚度基本上小于热氧化物的厚度。 在目前优选的实施例中，场氧化物的厚度为2,000至8,000埃，而薄氧化物的厚度小于300埃。

公开(公告)号：WO1998008254A1

公开(公告)日：1998-02-26

申请号：PCT/US1997009638

申请日：1997-05-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N.

IPC: H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/823857 ,  Y10S438/981

Abstract: A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N2O, NH3, O2 and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O2 and HCl in an approximate ratio of 90:7:3 or N2O, O2 and HCl in a approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region (102) may alternatively be accomplished with rapid thermal anneal processing.

Abstract translation: 一种用于在集成电路内产生两个栅极氧化物厚度的半导体工艺，其中提供具有第一区域和第二区域的半导体衬底。 第一区域和第二区域相对于彼此横向移位。 然后将氮物质杂质分布引入半导体衬底的第一区域。 此后，在半导体衬底的上表面上生长栅极电介质层。 栅极电介质在半导体衬底的第一区域上具有第一厚度，并且在半导体衬底的第二区域上具有第二厚度。 第一厚度小于第二厚度。 在本发明的CMOS实施例中，半导体衬底的第一区域包括p型硅，而第二衬底区域包括n型硅。 优选地，将氮物质杂质分布引入半导体衬底的步骤是通过在含氮环境中热氧化第一衬底区域来实现的。 在目前优选的实施方案中，含氮环境包括大约比例为60:30:7:3的N2O，NH3，O2和HCl。 在替代实施方案中，含氮环境包括大约比例为90:7:3的NO，O 2和HCl，或大约比例为90:7:3的N2O，O2和HCl。 可以通过快速热退火处理来实现将氮杂质引入到第一衬底区域（102）中。

公开(公告)号：WO1997049129A1

公开(公告)日：1997-12-24

申请号：PCT/US1997002492

申请日：1997-02-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N. ,  FULFORD, H., Jim, Jr.

IPC: H01L21/76

CPC classification number: H01L21/823418 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823481 ,  Y10S257/90

Abstract: A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.

Abstract translation: 一种用于隔离半导体器件的方法，包括提供半导体衬底。 半导体衬底包括横向移位的源极/漏极区域和沟道区域。 第一和第二侧向移位的MOS晶体管部分地形成在半导体衬底内。 第一和第二晶体管具有公共源极/漏极区域。 通过公共源极/漏极区域形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得公共源极/漏极区域被划分为电隔离的第一和第二源极/漏极区域，由此第一晶体管与 第二晶体管。

公开(公告)号：WO1996031904A1

公开(公告)日：1996-10-10

申请号：PCT/US1996000971

申请日：1996-01-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHANG, Kuang-Yeh ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N.

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/7833

Abstract: After growth of a thin oxide on a silicon semiconductor body, and formation of a gate thereover, a blanket layer of oxide is deposited over the resulting structure, this oxide layer having, as measured from the surface of the silicon body, relatively thick regions adjacent the sides of the gate and relatively thin regions extending therefrom. Upon implant of ions, the relatively thick regions block ions from passing therethrough into the semiconductor body, while the relatively thin regions allow passage of ions therethrough into the body. After drivein of the ions, the thick layer of oxide is isotopically etched to take a substantially uniform layer therefrom over the entire surface of the thick oxide layer, so that the thick regions thereof are reduced in width. Upon a subsequent ion implant step, the thick regions, now reduced in width from the sides of the gate, block passage of ions therethrough, while the thin regions allow ions therethrough into the silicon body. This process may be continued as chosen to form desired source and drain profile.

Abstract translation: 在硅半导体本体上生长薄氧化物并在其上形成栅极之后，在所得结构上沉积氧化物覆盖层，该氧化物层具有从硅体表面测量的较厚的相邻区域 门的侧面和从其延伸的相对薄的区域。 在离子注入时，相对较厚的区域阻止离子通过其进入半导体本体，而较薄的区域允许离子通过其进入体内。 在离子的驱动之后，厚厚的氧化物层被同位素蚀刻以在厚氧化物层的整个表面上从其中获得基本均匀的层，使得其厚的区域的宽度减小。 在随后的离子注入步骤中，现在从栅极的侧面减小宽度的厚区域阻止离子通过其中，而薄区域允许离子通过其进入硅体。 该过程可以根据选择继续以形成所需的源极和漏极分布。

公开(公告)号：WO1998025182A1

公开(公告)日：1998-06-11

申请号：PCT/US1997022616

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70241

Abstract: A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

Abstract translation: 掩模版（130）提供图像图案并补偿光刻系统中的透镜误差。 使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。 通过调节辐射透射区域（132,134）的配置（或布局），例如通过调节石英基底的顶表面上的铬图案，可以对掩模版进行结构上的修改。 或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。 图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。