公开(公告)号：WO2004095561A1

公开(公告)日：2004-11-04

申请号：PCT/US2003/041186

申请日：2003-12-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  GRAETSCH, Falk ,  HERRMANN, Lutz

IPC: H01L21/3115

CPC classification number: H01L21/28202 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/3144 ,  H01L29/518

Abstract: The present invention provides a technique for forming extremely thin insulation layers requiring the incorporation of specified amounts of nitrogen, wherein the effect of nitrogen variations across the substrate surface may be reduced in that during and/or after the nitrogen incorporation an oxidation process is performed. The nitrogen variations lead to a nitrogen concentration dependent oxidation rate and, hence, a nitrogen concentration dependent thickness variation of the insulating layer. In particular, the threshold variations of transistors including the thin insulating layer as a gate insulation layer may effectively be reduced.

Abstract translation: 本发明提供了一种形成极薄绝缘层的技术，该绝缘层需要结合规定量的氮，其中可以减少跨越衬底表面的氮变化的影响，因为在氮掺入期间和/或之后进行氧化过程。 氮变化导致氮浓度依赖的氧化速率，因此导致绝缘层的氮浓度依赖性厚度变化。 特别地，可以有效地降低包括作为栅极绝缘层的薄绝缘层的晶体管的阈值变化。

公开(公告)号：WO2005098929A2

公开(公告)日：2005-10-20

申请号：PCT/US2005/010475

申请日：2005-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  LENSKI, Markus ,  GRAETSCH, Falk ,  REICHEL, Carsten ,  SCHWAN, Christoph ,  BIERSTEDT, Helmut ,  KAMMLER, Thorsten ,  MAZUR, Martin

Inventor： LENSKI, Markus ,  GRAETSCH, Falk ,  REICHEL, Carsten ,  SCHWAN, Christoph ,  BIERSTEDT, Helmut ,  KAMMLER, Thorsten ,  MAZUR, Martin

IPC: H01L21/336

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

Abstract: The present invention allows the formation of sidewall spacers (217,218) adjacent a feature (206) on a substrate (201) without there being an undesirable erosion of the feature. The feature (206) is covered by one or more protective layers (220,207). A layer of a spacer material (211) is deposited over the feature (206) and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers (220, 207) are substantially not affected by the etchant. Thus, the one or more protective layers (220, 207) protect the feature from being exposed to the etchant.

Abstract translation: 本发明允许在衬底（201）上邻近特征（206）形成侧壁间隔物（217,218），而不会有不希望的特征侵蚀。 特征（206）由一个或多个保护层（220,207）覆盖。 隔离材料层（211）沉积在特征（206）上并各向异性地蚀刻。 在各向异性蚀刻中使用的蚀刻剂适于选择性地去除间隔物材料，而一个或多个保护层（220,207）基本上不受蚀刻剂的影响。 因此，一个或多个保护层（220,207）保护特征不暴露于蚀刻剂。

公开(公告)号：WO2003073491A1

公开(公告)日：2003-09-04

申请号：PCT/US2002/040807

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  GRAETSCH, Falk ,  KRUEGEL, Stephan

IPC: H01L21/311

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

Abstract: A method of forming oxide layers of different thickness on a substrate (1) is disclosed, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices

Abstract translation: 公开了一种在基板（1）上形成不同厚度的氧化物层的方法，其中氧化物层优选用作场效应晶体管的栅极绝缘层。 与常规处理相比，该方法允许形成具有减少数量的掩模步骤的非常薄的高质量氧化物层，其中厚度差可以保持在十分之几纳米的范围内。 该方法基本上消除了任何高温氧化，并且也与用于复杂半导体器件中的栅极介电沉积的大多数化学气相沉积技术相兼容

公开(公告)号：EP1476899A1

公开(公告)日：2004-11-17

申请号：EP02787067.4

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  GRAETSCH, Falk ,  KRUEGEL, Stephan

IPC: H01L21/311 ,  H01L21/318 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/314

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

Abstract: A method of forming oxide layers of different thickness on a substrate (1) is disclosed, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices

公开(公告)号：EP1476899B1

公开(公告)日：2007-03-07

申请号：EP02787067.4

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  GRAETSCH, Falk ,  KRUEGEL, Stephan

IPC: H01L21/311 ,  H01L21/318 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/314

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

Abstract: A method of forming oxide layers of different thickness on a substrate (1) is disclosed, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices