公开(公告)号：WO2008127643A2

公开(公告)日：2008-10-23

申请号：PCT/US2008/004692

申请日：2008-04-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  PAN, James, N. ,  SUN, Sey-Ping ,  WAITE, Andrew, M.

Inventor： PAN, James, N. ,  SUN, Sey-Ping ,  WAITE, Andrew, M.

IPC: H01L21/336

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  Y10S438/938 ,  H01L2924/00

Abstract: A strain enhanced semiconductor device 30 and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material 102, 106 in the source 103, 107 and drain 105, 109 regions of the device to induce a strain in the device channel 70, 72. Thin metal suicide contacts 112 are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material 114, 116 is selectively deposited in contact with the thin metal suicide contacts, and metallized contacts 22 are formed to the conductive material.

Abstract translation: 提供了应变增强半导体器件30及其制造方法。 一种方法包括将应变诱导半导体材料102,106嵌入在器件通道70,72的源极103,107和漏极105,109区域中以引起应变。薄金属硅化物触点112形成于源极 漏区，以免减轻诱发应变。 选择性地沉积与薄金属硅化物触点接触的导电材料层114,116，并且金属化触点22形成为导电材料。

公开(公告)号：WO2005112127A1

公开(公告)日：2005-11-24

申请号：PCT/US2005/013239

申请日：2005-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  SUN, Sey-Ping ,  BROWN, David, E.

Inventor： SUN, Sey-Ping ,  BROWN, David, E.

IPC: H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

Abstract: The carrier mobility in transistor channel regions of Si-Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively (90) or high tensilely (120) stressed film, after post silicide spacer removal, over gate electrodes (72) and strained Si source/drain regions (71) of P-channel or N-channel transistors, respectively.

Abstract translation: Si-Ge器件的晶体管沟道区域中的载流子迁移率通过使用应力衬里来增加。 实施例包括施加覆盖松弛的源极/漏极区域的高压缩或拉伸应力膜。 其他实施方案包括在硅化硅间隔物去除之后，在P沟道或N沟道晶体管的栅电极（72）和应变Si源极/漏极区（71）上施加高压缩（90）或高拉伸（120）应力膜 ， 分别。

公开(公告)号：WO2002099857A1

公开(公告)日：2002-12-12

申请号：PCT/US2002/011555

申请日：2002-04-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUN, Sey-Ping ,  BROWN, David, E. ,  LAM, Kin-Sang

IPC: H01L21/027

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/32139

Abstract: A circuit device (36, 38) incorporating an anti-reflective coating (26) and methods of fabricating the same are provided. In one aspect, a method of processing a substrate (10) is provided that includes forming a film (16) on the substrate (10) and forming an anti-reflective coating (16) on the film (16) by first forming a silicon-rich nitride film (26) on the film (16) in a first plasma atmosphere (28) and thereafter exposing the silicon-rich nitride film (26) in-situ to a second plasma atmosphere (32) containing oxygen to convert an upper portion of the silicon-rich nitride film (26) to silicon oxynitirde. Variability in the optical properties of the anti-reflective coating is substantially reduced, resulting in improved UV lithographic patterning of etch masking.

Abstract translation: 提供了包括抗反射涂层（26）的电路装置（36,38）及其制造方法。 一方面，提供了一种处理衬底（10）的方法，其包括在衬底（10）上形成膜（16）并且在膜（16）上形成抗反射涂层（16），首先形成硅 在第一等离子体气氛（28）中的膜（16）上的富氮氮化物膜（26），然后将富含硅的氮化物膜（26）原位暴露于含有氧的第二等离子体气氛（32），以将上部 富含硅的氮化物膜（26）的一部分与硅氧氮化物反应。 防反射涂层的光学性能的变化性大大降低，从而改进了蚀刻掩模的UV光刻图案。

公开(公告)号：EP1135796B1

公开(公告)日：2006-05-31

申请号：EP99930309.2

申请日：1999-06-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUN, Sey-Ping ,  GARDNER, Mark, I. ,  NGO, Minh, Van

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/3145 ,  H01L21/76828 ,  H01L21/76834

Abstract: An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use un integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deoposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.

公开(公告)号：EP0960437A1

公开(公告)日：1999-12-01

申请号：EP98919791.0

申请日：1998-04-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： NGO, Minh, Van ,  CHAN, Darin, A. ,  SUN, Sey-Ping ,  KITSON, Terri ,  CAFFALL, John

IPC: H01L21

CPC classification number: H01L21/76801 ,  H01L21/3144 ,  H01L21/76834 ,  H01L21/76895

Abstract: The method includes depositing a thin SiOxNy stop layer (22') on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber having a low pressure, maintaining the low pressure following the deposition of the SiOxNy stop layer, and then depositing a thick TEOS oxide dielectric layer (26') on the SiOxNy stop layer (22') within the CVD reactor chamber.

公开(公告)号：EP1133788A1

公开(公告)日：2001-09-19

申请号：EP99930795.2

申请日：1999-06-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUN, Sey-Ping ,  VAN NGO, Minh

IPC: H01L21/027 ,  G03F7/09

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/3105 ,  H01L21/32139

Abstract: A silane-based oxide (40) having a thickness of about 300 nm or less is formed for use in an anti-reflective coating for patterning metal interconnects having small dimensions (e.g., 0.18 micron or less) and large aspect ratios. The oxide (40) is formed in such a way that it does not react with a popular deep ultraviolet photoresist (38). The reaction, known as 'footing' (18), can result in a loss of the intended feature dimensions. In one embodiment of the method, the silane-based oxide (40) is deposited using a non-nitrogen carrier gas for the silane. In an alternate embodiment, a nitrogen carrier gas is used and the oxide (40) is subsequently exposed to an N2O plasma (2). The resulting oxide (40) can be made using a low-cost, high-throughput, and low-defect process as compared to other oxide formation methods.

公开(公告)号：EP1135796A1

公开(公告)日：2001-09-26

申请号：EP99930309.2

申请日：1999-06-16

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUN, Sey-Ping ,  GARDNER, Mark, I. ,  NGO, Minh, Van

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/3145 ,  H01L21/76828 ,  H01L21/76834

Abstract: An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use un integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deoposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.