公开(公告)号：JPH02138879A

公开(公告)日：1990-05-28

申请号：JP29213788

申请日：1988-11-18

Applicant: ADVANTEST CORP

Inventor： CHIYOMURA YUUZOU

IPC: G01D3/02 ,  G01R15/00 ,  G06F1/02 ,  H03B28/00 ,  H03K4/02 ,  H03K4/94 ,  H03L3/00

Abstract: PURPOSE:To reduce a burden of CPU by providing an incremental/decremental counter, a first flip-flop triggered by an ON signal and a second flip-flop triggered by an OFF signal. CONSTITUTION:When an incremental/decremental counter 25 reaches a full-scale value, this is detected by an all '1' detecting circuit 36, a first flip-flop 26 is cleared by a detection output of this circuit, and thereby a count increment mode is ended. Next, when an OFF signal is given from CPU to a terminal 29, a second flip-flop 27 is triggered, a Q output of the second flip-flop turns to be '1', a second gate 35 is thereby opened, and the incremental/decremental counter 25 conducts a count decrement operation. On the occasion, an output of an oscillator 38 is frequency-divided by a variable frequency division circuit 39, a divided frequency output thereof is synchronized with a sampling clock in a synchronization circuit 41, and a synchronized output thereof is supplied to first and second gates 34 and 35. According to this constitution, it is unnecessary to set taper data variously by the CPU and thus a burden of the CPU is reduced.

公开(公告)号：JPH02149107A

公开(公告)日：1990-06-07

申请号：JP30437688

申请日：1988-11-30

Applicant: ADVANTEST CORP

Inventor： CHIYOMURA YUUZOU ,  KASAHARA TOSHIHARU

IPC: H03B23/00 ,  H03B28/00

Abstract: PURPOSE:To dispense with the write of swept sine data on a RAM by a CPU by generating a swept sine wave by hardware constitution. CONSTITUTION:A value corresponding to the start frequency of a swept sine is stored in a first latch 21, and the value corresponding to the sweep rate of the swept sine is stored in a second latch 22. The output of the second latch 22 is added on that of a third latch 23 at a first adder 24, and the output of the first latch 21 and that of the first adder 24 are switched by a switch 25, then, it is stored in the third latch 23. The output of the third latch 23 is added on that of a fourth latch 26 at a second adder 27, then, it is stored in the fourth latch 26. And a control circuit 31 is controlled by the output of a presettable counter 29, and the control circuit 31 performs the switching of the switch, storage on the third latch, and the clear of the fourth latch. In such a way, no write on the RAM at every point by the CPU is required.

公开(公告)号：JPH01105183A

公开(公告)日：1989-04-21

申请号：JP26329187

申请日：1987-10-19

Applicant: ADVANTEST CORP

Inventor： YAMAGUCHI TAKAHIRO ,  ENOMOTO KOJI ,  OGAWA MASAYUKI ,  CHIYOMURA YUUZOU

IPC: G01R29/02 ,  G01R13/20 ,  H04L25/02

Abstract: PURPOSE:To measure the generation frequency of the variation width (jitter) of an eye pattern at a previously specified sampling point by inputting an input signal according to a dropout trigger as a reference. CONSTITUTION:The input signal is A/D-converted 12 and stored in a memory 13, and also inputted to the trigger deciding circuit 15 of a dropout trigger detecting means 14. The circuit 15 outputs '1' or '0' according to the trigger level of the input signal and the signal is converted by a series-parallel converting circuit 16 into a parallel signal by every N bits and supplied to a comparator 17. The comparator 17 inputs N-bit dropout patterns from a dropout pattern register 18 and those inputs are compared. Then every time the comparator 17 generates a dropout trigger, a CPU 21 detects the maximum and minimum values at each sampling point in a digital signal passed through a processing memory 22 and finds the generation frequency of the digital signal value at the previously specified sampling point.