公开(公告)号：JPS6285464A

公开(公告)日：1987-04-18

申请号：JP22370285

申请日：1985-10-09

Applicant: AGENCY IND SCIENCE TECHN

Inventor： MUTO SHUNICHI

IPC: H01L29/68 ,  H01L29/20

Abstract: PURPOSE:To obtain an HET having large current density by using a multiplex hetero junction of AlGaAs and GaAs in a barrier layer between an emitter and a base to form a graded potential barrier layer remarkably thinner than the conventional one. CONSTITUTION:A barrier layer 5 is formed of multiplex hetero junction. In other words, 3 layers of AlGaAs layers 9, 10, 11 are interposed between non- doped GaAs layers 12 and 13 to be laminated in a sandwich shape so that the thicknesses of the AlGaAs layers are 20Angstrom and the thicknesses of the layers 12, 13 are 10 and 40Angstrom , respectively. The total thickness of the potential barrier layer is 110Angstrom to be remarkably smaller than approx. 300Angstrom of the conventional graded potential layer, with the result that the current density from the emitter layer is significantly improved from a conventional structure.

公开(公告)号：JPS61268062A

公开(公告)日：1986-11-27

申请号：JP10936585

申请日：1985-05-23

Applicant: AGENCY IND SCIENCE TECHN

Inventor： INADA TSUGUO ,  MUTO SHUNICHI

IPC: H01L29/26 ,  H01L29/205 ,  H01L29/68 ,  H01L29/76

Abstract: PURPOSE:To improve electron amplification-factor characteristics by applying negative bias voltage to a collector electrode to a base electrode, passing electrons through a second barrier layer and a base layer from an emitter layer and making electrons to reach a collector layer through a first barrier layer. CONSTITUTION:An N-type GaAs collector contact layer 2, an N-type GaAs collector layer 3, a non-doped AlGaAs barrier layer 4, a base layer 5, a non- doped AlGaAs barrier layer 6, an N-type GaAs emitter layer 7 and an N-type GaAs emitter contact layer 8 are laminated on a substrate 1. A collector electrode 10 consisting of AuGe/Au, a base electrode 11 and an emitter electrode 12 are formed brought into contact with the layer 2, the layer 5 and the layer 8, bias voltage, which brings the electrode 12 to negative potential to the electrode 11 and the electrode 11 to negative potential to the electrode 10, is applied, and electrons punches through the layer 6 from the layer 7 by a tunnel effect, pass through the layer 5, and cross the potential level of the layer 4 and are made to reach the layer 3. Accordingly, characteristics such as a current amplification factor can be improved.

公开(公告)号：JPS63127577A

公开(公告)日：1988-05-31

申请号：JP27289186

申请日：1986-11-18

Applicant: AGENCY IND SCIENCE TECHN

Inventor： INADA TSUGUO ,  MUTO SHUNICHI

IPC: H01L47/00 ,  H01L29/201 ,  H01L29/88

Abstract: PURPOSE:To combine large peak current density and a current density ratio by injecting electrons to a quantum well structure from a second n-type gallium arsenide layer. CONSTITUTION:A resonance tunneling barrier diode has a structure in which n-type GaAs layers 2, 8 as injection electronic sources are grown onto AlGaAs/ GaAs/AlGaAs quantum well structure in an epitaxial manner, interposing a second non-doped GaAs layer 6 and a third non-doped AlGaAs layer 7. The interposed non-doped AlGaAs/GaAs hetero-junction has an effect of obstructing the diffusion of an impurity such as Si introduced to the n-type GaAs layers 2, 8 as the injection electronic sources, and a remarkable impurity-diffusion preventive effect is acquired even when the AlGaAs layer 7 consists of one or two atomic layer and the GaAs layer 6 is shaped in approximately 10Angstrom . The shape of the transmission coefficient of a resonance tunneling barrier hardly changes even when the AlGaAs/GaAs hetero-junction thin in this extent is interposed, and valley current density JV is reduced largely without minimizing peak current density JP, thus remarkably improving a maximum/minimum current density ratio JP/JV.

公开(公告)号：JPS627158A

公开(公告)日：1987-01-14

申请号：JP14457185

申请日：1985-07-03

Applicant: AGENCY IND SCIENCE TECHN

Inventor： MUTO SHUNICHI

IPC: H01L29/205 ,  H01L21/28 ,  H01L29/20 ,  H01L29/68 ,  H01L29/76

Abstract: PURPOSE:To remove the restriction of forming a base contact by etching a collector layer in a mesa shape, growing a nondoped buried layer on the region to form an HET operating region and a collector layer in a range of a stripe necessary to lead the collector electrode. CONSTITUTION:An N-type GaAs collector layer 3 is epitaxially grown through a nondoped GaAs buffer layer 2 on a semi-insulating GaAs substrate 1, a mask 4 is formed thereon, etched, and the layer 3 is grown in a striped mesa shape. A nondoped GaAs buried layer 5 is grown in the height equal to the layer 3, the first A GaAs barrier 6, a GaAs base layer 7, the second A GaAs barrier layer 8 and an N-type GaAs emitter layer 9 are sequentially laminated and grown. The layer 9 is etched, and an emitter region 9E is formed on the region displaced toward any one of the layer 3. A collector electrode 10 is formed on a region near the opposite direction of the region 9E of the layer 3, and a base electrode 11 is formed on the layer 4, and an emitter electrode 12 is formed in contact with the region 9E.

公开(公告)号：JPS62176162A

公开(公告)日：1987-08-01

申请号：JP1670086

申请日：1986-01-30

Applicant: AGENCY IND SCIENCE TECHN

Inventor： MUTO SHUNICHI

IPC: H01L29/68 ,  H01L29/06 ,  H01L29/15 ,  H01L29/20 ,  H01L29/76 ,  H01L29/86

Abstract: PURPOSE:To obtain a negative resistance element, whose negative resistance value can be modulated and controlled from the outside, by providing a supper-lattice layer comprising aluminum arsenide and gallium arsenide between the base and the collector of a hot electron transistor, whose emitter and collector comprise one-conductivity type gallium arsenide layers and base comprises a non-doped aluminum gallium arsenide layer. CONSTITUTION:A one-conductivity type GaAs first conductor layer 5, a barrier layer 2, in which a plurality of sets of AlAs and GaAs layers are laminated, a one-conductivity type GaAs third semiconductor layer 3, a non-doped AlGaAs second barrier layer 2 and a one- conductivity type GaAs second semiconductor layer 1 are sequentially contacted and laminated. The first conductor layer 5 is contacted with a first electrode 9. The second semiconductor layer 1 is contacted with a second electrode 6. The third semiconductor layer 3 is contacted with a control electrode 7. A negative resistance element is formed in this way. A current Ic, which flows between the semiconductor layers 1 and 3, varies depending on both a voltage VEB between them and a voltage VBC between the semiconductor layers 3 and 5. The negative resistance characteristic is provided between a point, where the VEB (which determines the kinetic energy of hot electrons) corresponds to a value in a mini-band, and a slightly higher value of the VEB. The negative resistance characteristic can be externally modulated with the VBC.

公开(公告)号：JPS62137867A

公开(公告)日：1987-06-20

申请号：JP27801285

申请日：1985-12-12

Applicant: AGENCY IND SCIENCE TECHN

Inventor： MUTO SHUNICHI

IPC: H01L29/68 ,  H01L29/20 ,  H01L29/76

Abstract: PURPOSE:To prevent the electrons, entering a base layer tunneling through a barrier layer from an emitter layer, from passing the AlGaAs layer having no barrier effect by a method wherein a non-doped GaAs layer is provided between an Al0.3Ga0.7As barrier layer and a GaAs base layer located on the emitter side, and the potential inclination by emitter bias is formed by the Al0.3Ga0.7As barrier layer and the GaAs layer. CONSTITUTION:An N-type GaAs collector layer 2, an AlGaAs barrier layer 3, an N-type GaAs base layer 4, a GaAs layer 5, an AlGaAs barrier layer 6 and an N-type GaAs emitter layer 7 are epitaxially grown successively on an N-type GaAs substrate 1. Then, an emitter region is defined by selectively performing an etching treatment on the layers 5 and 7. Subsequently, an emitter electrode 10, a base electrode 9 and a collector electrode 8 are provided using gold-germanium-gold. The layer 6 or the layer 5 is normally formed in such a manner that the thickness of the lower end of the conduction band becomes equal to the Fermi level EFE of the layer 7 in the vicinity of the interface between the layers 6 and 5 when the prescribed emitter bias VBE is applied.

公开(公告)号：JPS627157A

公开(公告)日：1987-01-14

申请号：JP14457085

申请日：1985-07-03

Applicant: AGENCY IND SCIENCE TECHN

Inventor： INADA TSUGUO ,  MUTO SHUNICHI

IPC: H01L29/205 ,  H01L29/20 ,  H01L29/68 ,  H01L29/76

Abstract: PURPOSE:To deeply form without contacting a base contacting region at later step by forming a semi-insulating grown layer on a substrate, forming in advance a collector of the size matched to an emitter, and selectively burying a collector layer by the regrowth to form an HET. CONSTITUTION:An I-type GaAs layer 2 is grown on an N type GaAs substrate 1, and N-type dopant 4 is ion implanted selectively to form a collector region 5. After heat treating, a barrier layer of nondoped AlxGa1-xAs 6, a base layer of N-type GaAs 7, a barrier layer of nondoped AlxGa1-xAs 8, an emitter layer of N-type GaAs 9, and an emitter contacting layer of N type GaAs 10 are sequentially grown. After growing, a photolithography is performed by matching to the ion implanting region of the lower portion, and selectively etched to expose the base 7. Si or Se 12 is ion implanted to form a base contacting region 13. The depth of the region 13 by the ion implantation is stopped in the midway of the layer 2, and performed under the conditions for sufficiently obtaining a withstand voltage between the base and the collector.

公开(公告)号：JPS61268061A

公开(公告)日：1986-11-27

申请号：JP10936485

申请日：1985-05-23

Applicant: AGENCY IND SCIENCE TECHN

Inventor： IMAMURA KENICHI ,  YOKOYAMA NAOKI ,  MUTO SHUNICHI ,  INADA TSUGUO

IPC: H01L29/205 ,  H01L29/68 ,  H01L29/76

Abstract: PURPOSE:To prevent the lowering of withstanding voltage between a collector and a base by forming an electron supply layer combining a potential-barrier on the N-type AlGaAs emitter side and a base electrode being in contact with a GaAs base layer. CONSTITUTION:An N type GaAs emitter layer 17 is etched until it reaches an N-type AlGaAs etching stopping layer 17' while using an emitter electrode 19 as a mask. The layer 17' is removed, a base electrode 20 is shaped, and the residual layer 17 is etched until the etching reaches an electron supply layer 16 combining a potential-barrier on the N-type AlGaAs emitter side while employing the electrode 20 as a mask, thus forming a collector electrode 21 being in contact with an N-type collector region 13. Consequently, a two-element electron gas layer is formed in a GaAs base layer 15 at a low temperature even when the layer 15 is shaped in approximately 100-200Angstrom , thus increasing both carrier concentration and carrier-mobility. Accordingly, the lowering of withstand voltage between a collector and a base can be prevented.