公开(公告)号：JP2005124210A

公开(公告)日：2005-05-12

申请号：JP2004301119

申请日：2004-10-15

Applicant: Agilent Technol Inc ,  アジレント・テクノロジーズ・インクAgilent Technologies, Inc.

Inventor： ILNICKI SLAWOMIR K ,  KHOCHE AJAY ,  STEINBACH GUNTER W

IPC: H04L12/56 ,  H04L13/08 ,  H04L29/08

CPC classification number: H04L47/10 ,  H04L47/13 ,  H04L47/28 ,  H04L49/90 ,  H04L49/901

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for forming a low bandwidth channel in a high bandwidth channel. SOLUTION: The low bandwidth channel is formed in the high bandwidth channel. The low bandwidth channel is formed by inserting an extra packet by utilizing an excess bandwidth of the high bandwidth channel. When a gap of an internal packet that is at a suitable interval is detected, the extra packet is inserted and some arrival packets in the high bandwidth channel are stored in a buffer. The gap of the internal packets is monitored and a minimum delay is introduced in the high bandwidth channel when no extra packet exists in a transmission process. Thereby, a transmission packet on the low bandwidth channel is absorbed and dispersed among other passing traffics. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供一种用于在高带宽信道中形成低带宽信道的方法和装置。

解决方案：低带宽信道形成在高带宽信道中。 通过利用高带宽信道的超额带宽插入额外的分组来形成低带宽信道。 当检测到以适当间隔的内部分组的间隙时，插入额外分组，并将高带宽信道中的一些到达分组存储在缓冲器中。 监视内部分组的间隙，并且在传输过程中不存在额外分组时，在高带宽信道中引入最小延迟。 因此，低带宽信道上的传输分组被吸收并分散在其他传输流量中。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004184413A

公开(公告)日：2004-07-02

申请号：JP2003402477

申请日：2003-12-02

Applicant: Agilent Technol Inc ,  アジレント・テクノロジーズ・インクAgilent Technologies, Inc.

Inventor： VOLKERINK ERIK H ,  KHOCHE AJAY ,  HILLIGES KLAUS D

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3183

CPC classification number: G01R31/318335 ,  G01R31/31705 ,  G01R31/318307

Abstract: PROBLEM TO BE SOLVED: To provide a system and method saving the data storage capacity required for a tester (for example, an automatic tester) and minimizing the on-chip circuit quantity required for such a test. SOLUTION: This system includes a means 302 for inputting test data into a chip 315 to be tested, a means 303 for receiving output data from the chip to be tested in response to the input test data, a means 305 for generating a signature for at least part of the received output data, a means 306 for comparing the generated signature to an expected signature, and a means 307 for storing information into an error map log when the generated signature does not coincide with the expected signature. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种节省测试仪（例如自动测试仪）所需的数据存储容量并最小化这种测试所需的片上电路数量的系统和方法。 解决方案：该系统包括用于将测试数据输入到要测试的芯片315中的装置302，用于响应于输入的测试数据从待测试的芯片接收输出数据的装置303，用于生成 对于所接收的输出数据的至少一部分的签名，用于将生成的签名与预期签名进行比较的装置306，以及当所生成的签名与预期签名不一致时将信息存储到错误映射日志中的装置307。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004117352A

公开(公告)日：2004-04-15

申请号：JP2003322477

申请日：2003-09-16

Applicant: Agilent Technol Inc ,  アジレント・テクノロジーズ・インクAgilent Technologies, Inc.

Inventor： KHOCHE AJAY

IPC: G01R31/28 ,  G01R31/317 ,  H01L21/66

CPC classification number: G01R31/31707

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for multipoint testing wherein different test sequence is applied to each parallel-tested die.
SOLUTION: In this method, heterologous test sequence is adopted for a parallel-tested die. Sequence for testing circuit block of discrete die is selected in order to optimize testing time of a set of dies to be parallel-tested. Further, or instead, the sequence for testing circuit block of discrete die is selected so as to manage or reduce the test resource used for testing of dies. Additionally the test sequence is dynamically determined for the die of a set of parallel-tested ones in response to feedback from a sensor monitoring the die in order to meet various secondary effects.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003179149A

公开(公告)日：2003-06-27

申请号：JP2002259142

申请日：2002-09-04

Applicant: AGILENT TECHNOLOGIES INC

Inventor： KHOCHE AJAY ,  RIVOIR JOCHEN ,  ARMSTRONG DAVID H

IPC: G01R31/28 ,  G01R31/3185 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method for performing a test to be conducted on an IC with the possibility of resetting one of scan architectures and with a high degree of accuracy and failure detection range and in the shortest time. SOLUTION: With respect to the method for setting an integrated circuit (200), which is provided with several integrated circuit input/output pins having specified maximum input/output frequency and several scan chains (208) which are electrically conductive with the input/output pins for a test, the scan chains have the specified maximum latching frequency and the integrated circuit is connected to an integrated circuit testing device via a usable number of pins of the several integrated circuit input/output pins. The method includes a step for setting the time for testing the integrated circuit to the shortest when the latch frequency is lower than the specified maximum input/output frequency and the number of available integrated circuit input/output pins is smaller than that, which is required by the presented scan architecture (202). COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002311111A

公开(公告)日：2002-10-23

申请号：JP2002063298

申请日：2002-03-08

Applicant: AGILENT TECHNOLOGIES INC

Inventor： KHOCHE AJAY ,  RIVOIR JOCHEN

IPC: G01R31/3183

Abstract: PROBLEM TO BE SOLVED: To provide a method of compressing test vectors used in ATE at a high efficiency. SOLUTION: The method comprises a step (104) of generating a random sequence having at least the same number of elements as a test vector, a step (106) of segmenting the test vector into a plurality of test vector element segments one after another wherein at least one of the test vector segments has 'don't care' value, a step (106) of segmenting the random sequence into a plurality of random sequence element segments corresponding to the test vector segments, a step (108) of comparing the test vector segments with corresponding segments of the random sequence one after another to determine if pairs of the test vector segments and the random sequence segments coincide, a step (100a) of compressing the test vector by inserting different flag values to coincident corresponding segment pairs and not coincident corresponding segment pairs, and a step (100b) of canceling the compression of the compressed test vector, into a complete designation test vector, based on the different flag value.

公开(公告)号：WO2006076114A3

公开(公告)日：2009-04-16

申请号：PCT/US2005045222

申请日：2005-12-14

Applicant: AGILENT TECHNOLOGIES INC

Inventor： O'NEILL PETER M ,  KHOCHE AJAY

IPC: G06F17/50 ,  G06F9/44 ,  G06F9/455 ,  G06G7/62

CPC classification number: G06Q99/00 ,  G06Q10/067

Abstract: A multi-component production devices in accordance with a device design having performance specifications is made by a method comprising receiving (110) respective component behavioral models of the production components constituting the production device; combining (112) the component behavioral models in accordance with the device design to form a device behavioral model; and, prior to assembling the production device, predicting (114) performance metrics for the production device by performing simulated tests on the device behavioral model.

Abstract translation: 根据具有性能规格的设备设计的多部件生产设备通过以下方法进行：包括接收（110）构成生产设备的生产部件的各个部件行为模型; 根据设备设计组合（112）组件行为模型以形成设备行为模型; 并且在组装生产设备之前，通过对设备行为模型进行模拟测试来预测（114）生产设备的性能指标。

公开(公告)号：WO2006076117A3

公开(公告)日：2007-02-01

申请号：PCT/US2005045278

申请日：2005-12-14

Applicant: AGILENT TECHNOLOGIES INC

Inventor： KHOCHE AJAY ,  TUFILLARO NICHOLAS B ,  JEFFERSON STANLEY T ,  BARFORD LEE A

IPC: G06F17/50 ,  G06F7/60 ,  G06F19/00

CPC classification number: G01R31/319 ,  G01R31/31917 ,  G01R31/3193

Abstract: The model-based method tests compliance of production devices with the performance specifications of a device design. The production devices are manufactured in accordance with the device design by a manufacturing process. In the method, a simple model form based on the device design and the performance specifications is developed (212), a stimulus for testing the production devices is specified (214) and each production device is tested (220). The model form has a basis function and model form parameters for the basis function. The model form parameters are dependent on the manufacturing process and differ in value among the production devices. A production device is tested by measuring (222) the response of the production device to the stimulus; extracting (224), using the model form, the values of the model form parameters for the production device from the measured response and the stimulus; and checking (226) compliance of the production device with the performance specifications using the extracted values of the model form parameters.

Abstract translation: 基于模型的方法测试生产设备的符合性与设备设计的性能规格。 生产设备根据制造过程的设备设计制造。 在该方法中，开发了基于设备设计和性能规范的简单模型（212），指定了对生产设备进行测试的刺激（214），并对每个生产设备进行了测试（220）。 模型形式具有基函数和基函数的模型形式参数。 模型形式参数取决于制造过程，并且生产装置之间的价值不同。 通过测量（222）生产设备对刺激的响应来测试生产设备; 使用模型形式从测量的响应和刺激中提取（224）生产设备的模型形式参数的值; 以及使用提取的模型形式参数的值来检查（226）生产设备的符合性和性能规范。

公开(公告)号：DE602004006573D1

公开(公告)日：2007-07-05

申请号：DE602004006573

申请日：2004-09-23

Applicant: AGILENT TECHNOLOGIES INC

Inventor： ILNICKI SLAWOMIR K ,  KHOCHE AJAY ,  STEINBACH GUNTER W

IPC: H04L12/56 ,  H04L13/08 ,  H04L29/08

Abstract: Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra packet is inserted and any incoming packets on the high-bandwidth channel are stored in an elastic buffer. Observing inter-packet gaps, minimal latency is introduced in the high-bandwidth channel when there is no extra packet in the process of being sent, and the effects of sending a packet on the low-bandwidth channel are absorbed and distributed among other passing traffic.

公开(公告)号：DE602004006573T2

公开(公告)日：2008-01-31

申请号：DE602004006573

申请日：2004-09-23

Applicant: AGILENT TECHNOLOGIES INC

Inventor： ILNICKI SLAWOMIR K ,  KHOCHE AJAY ,  STEINBACH GUNTER W

IPC: H04L12/56 ,  H04L13/08 ,  H04L29/08

Abstract: Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra packet is inserted and any incoming packets on the high-bandwidth channel are stored in an elastic buffer. Observing inter-packet gaps, minimal latency is introduced in the high-bandwidth channel when there is no extra packet in the process of being sent, and the effects of sending a packet on the low-bandwidth channel are absorbed and distributed among other passing traffic.

公开(公告)号：GB2391706A

公开(公告)日：2004-02-11

申请号：GB0311342

申请日：2003-05-16

Applicant: AGILENT TECHNOLOGIES INC

Inventor： VOLKERINK ERIK H ,  KHOCHE AJAY

IPC: G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  G01R31/3187

Abstract: A system and method are disclosed in which a plurality of dice (21, 22) on a semiconductor wafer (20) are interconnected to enable efficient testing. Dice are interconnected (23) in a manner that enables test data to be communicated from a tester system (26) to a plurality of dice (21, 22) for concurrent testing of such plurality of dice. Depending on the amount of interconnection, all or a portion of each of the plurality of dice (21, 22) may be tested concurrently. The dice may be interconnected in a manner that enables test data to be communicated from one die to at least one other die. Dice (21, 22) may be interconnected in a manner that enables such dice to be tested concurrently while maintaining a repeatable pattern at the reticle level for fabricating such dice.