公开(公告)号：WO2011112579A3

公开(公告)日：2011-12-22

申请号：PCT/US2011027543

申请日：2011-03-08

Applicant: ALTERA CORP ,  DING WEIQI ,  PAN MINGDE

Inventor： DING WEIQI ,  PAN MINGDE

IPC: H03K3/023 ,  H03K5/08

CPC classification number: H03K3/356139 ,  H03K5/08

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract translation: 高速差分比较器电路具有精确可调的阈值电压。 提供差分参考电压信号来控制比较器的阈值电压。 参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

公开(公告)号：WO2012138509A3

公开(公告)日：2013-01-03

申请号：PCT/US2012030753

申请日：2012-03-27

Applicant: ALTERA CORP ,  DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  HOANG TIM TRI ,  KE YANJING

Inventor： DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  HOANG TIM TRI ,  KE YANJING

IPC: H04B1/04 ,  H03L7/00

CPC classification number: H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract translation: 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：WO2012037517A2

公开(公告)日：2012-03-22

申请号：PCT/US2011052028

申请日：2011-09-16

Applicant: ALTERA CORP ,  DING WEIQI ,  PAN MINGDE ,  LI PENG ,  SHUMARAYEV SERGEY ,  SHIMANOUCHI MASASHI

Inventor： DING WEIQI ,  PAN MINGDE ,  LI PENG ,  SHUMARAYEV SERGEY ,  SHIMANOUCHI MASASHI

IPC: H04L1/00 ,  G01R29/02

CPC classification number: H04L1/203 ,  G01R31/3171

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract translation: 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：WO2012021332A3

公开(公告)日：2012-04-12

申请号：PCT/US2011046239

申请日：2011-08-02

Applicant: ALTERA CORP ,  LI PENG ,  SHIMANOUCHI MASASHI ,  SHUMARAYEV SERGEY ,  DING WEIQI ,  NARAYAN SRIRAM ,  CHOW DANIEL TUN LAI ,  PAN MINGDE

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  SHUMARAYEV SERGEY ,  DING WEIQI ,  NARAYAN SRIRAM ,  CHOW DANIEL TUN LAI ,  PAN MINGDE

IPC: G01R31/303

CPC classification number: G01R31/31709 ,  G01R31/3171 ,  G01R31/31716 ,  H04L7/0337

Abstract: An integrated circuit ("IC") may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate ("BER") analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

公开(公告)号：WO2011119369A3

公开(公告)日：2011-11-24

申请号：PCT/US2011028465

申请日：2011-03-15

Applicant: ALTERA CORP ,  DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  ATESOGLU ALI ,  IPPILI SHARAT BABU

Inventor： DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  ATESOGLU ALI ,  IPPILI SHARAT BABU

IPC: H03L7/099 ,  H01F17/00

CPC classification number: H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively coupled to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be coupled to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor air in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract translation: 提供带锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，电压控制振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲器电路。 多个电感器中的选定的一个可以被主动地耦合到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以耦合到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲器电路中的相应输入晶体管空气。 通过向振荡器电路中选定的一个提供高电压，并通过向其余振荡器电路提供地电压，在正常操作期间，可以选择一个振荡器电路。

公开(公告)号：WO2010039444A2

公开(公告)日：2010-04-08

申请号：PCT/US2009057271

申请日：2009-09-17

Applicant: ALTERA CORP ,  XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

Inventor： XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

IPC: H01L27/088 ,  H01L21/265

CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

Abstract translation: 提出了一种使用正向偏置和改进的混合信号处理的电路设计来提高模拟电路性能的方法。 定义了由多个NMOS和PMOS晶体管组成的电路。 NMOS晶体管的体端耦合到第一电压源并且PMOS晶体管的体端耦合到第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的本体端子并且将第二电压源施加到每个选定的PMOS晶体管的本体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的本体端子提供正向和反向偏置。

公开(公告)号：WO2009126267A3

公开(公告)日：2010-01-14

申请号：PCT/US2009002188

申请日：2009-04-07

Applicant: ALTERA CORP ,  CHAN ALLEN ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  DING WEIQI

Inventor： CHAN ALLEN ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  DING WEIQI

IPC: H04L12/56

CPC classification number: H04L49/30 ,  H04L49/352

Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

Abstract translation: 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10吉比特以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

公开(公告)号：JP2009147948A

公开(公告)日：2009-07-02

申请号：JP2008320310

申请日：2008-12-16

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN ALLEN ,  SHUMARAYEV SERGEY ,  DING WEIQI

IPC: H03K19/0175 ,  H04L25/02

CPC classification number: H04L25/028

Abstract: PROBLEM TO BE SOLVED: To provide high-speed serial digital data signal transmitter driver circuitry.
SOLUTION: The present invention relates to transmitter driver circuitry for outputting a high-speed serial data signal having a serial bit rate in the range of about 10 Gbps, including H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor forming a portion of the H-tree driver circuitry further provides electrostatic discharge protection for the circuitry.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供高速串行数字数据信号发射器驱动电路。 解决方案：本发明涉及用于输出具有约10Gbps范围内的串行比特率的高速串行数据信号的发射机驱动器电路，包括仅具有主驱动级和后级的H树驱动器电路 tap驱动阶段。 形成H树驱动器电路的一部分的至少一个晶体管进一步为电路提供静电放电保护。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2013251916A

公开(公告)日：2013-12-12

申请号：JP2013161153

申请日：2013-08-02

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： DING WEIQI ,  LIU MENGCHI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H04L25/03 ,  H04B3/04

CPC classification number: H04L25/03878 ,  H04L7/0054

Abstract: PROBLEM TO BE SOLVED: To provide preferable and efficient data conversion processes between a high-speed serial data format and a parallel data format.SOLUTION: Receiver circuitry for receiving a high-speed serial data signal having a serial bit rate in the range of about 10 Gbps includes a two-stage continuous-time linear equalizer having only two stages connected in series. Each of the stages has a DC gain parameter which is variable, and a pole and/or a zero whose locations are variable in terms of the frequency. The DC gain parameter and the pole and/or zero locations of each stage are variable by programs.

Abstract translation: 要解决的问题：提供高速串行数据格式和并行数据格式之间优选和有效的数据转换处理。解决方案：接收电路，用于接收串行比特率在大约的范围内的高速串行数据信号 10Gbps包括仅具有串联连接的两级的两级连续时间线性均衡器。 每个级具有可变的DC增益参数，以及位置在频率方面可变的极点和/或零点。 每个阶段的直流增益参数和极点和/或零点位置都可以通过程序进行变化。

公开(公告)号：JP2009147947A

公开(公告)日：2009-07-02

申请号：JP2008320309

申请日：2008-12-16

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： DING WEIQI ,  LIU MENGCHI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H04L25/03 ,  H04B3/04 ,  H04L27/01

CPC classification number: H04L25/03878 ,  H04L7/0054

Abstract: PROBLEM TO BE SOLVED: To provide a data conversion process which can convert a serial data format to a parallel data format successfully and efficiently, and also to provide a data conversion process in the opposite direction. SOLUTION: The receiver circuitry for receiving high-speed serial data signals having serial bit rates in the range of about 10 Gbps includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Each of the stages has variable parameters of a DC gain, and a pole and/or zero whose location is variable with respect to frequency. The parameters of the DC gain at each stage and the locations of the pole and/or zero are variable by programs. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供可以成功且有效地将串行数据格式转换为并行数据格式的数据转换处理，并且还提供相反方向的数据转换处理。 解决方案：用于接收具有大约10Gbps范围内的串行比特率的高速串行数据信号的接收机电路包括仅具有两个串联连接级的两级连续时间线性均衡器。 每个级具有DC增益的可变参数，以及位置相对于频率可变的极点和/或零点。 每个阶段的直流增益参数和极点和/或零点的位置都可以通过程序来实现。 版权所有（C）2009，JPO＆INPIT