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    INTER-DEVICE COMMUNICATION INTERFACE
    1.
    发明申请
    INTER-DEVICE COMMUNICATION INTERFACE 审中-公开
    设备间通信接口

    公开(公告)号：WO0213072A2

    公开(公告)日：2002-02-14

    申请号：PCT/US0124786

    申请日：2001-08-07

    Applicant: ALTERA CORP

    Inventor： METZGEN PAUL

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5045 ,  G06F17/5054

    Abstract: A hardware-to-software compiler is provided that runs an optimization on a circuit implemented in programmable logic. The optimization allows portions of the program implemented by the circuit to be executed via software. A communication interface between the hardware and software is provided that allows for efficient data flow. A communication channel is provided that can be effected as bidirectional using a unidirectional transport medium (e.g., PCI bus). Communication between devices is done through pop interface buffers and push interface buffers on either side of the communication channel.

    Abstract translation: 提供了一种硬件到软件的编译器，可以在可编程逻辑中实现的电路上进行优化。 优化允许由电路实现的程序的部分通过软件执行。 提供硬件和软件之间的通信接口，允许有效的数据流。 提供可以使用单向传输介质（例如，PCI总线）作为双向实现的通信信道。 通过弹出界面缓冲区和通信通道两侧的推送接口缓冲区来实现设备之间的通信。

    INTER-DEVICE COMMUNICATION INTERFACE
    2.
    发明申请
    INTER-DEVICE COMMUNICATION INTERFACE 审中-公开
    设备间通信接口

    公开(公告)号：WO0213072A8

    公开(公告)日：2003-10-23

    申请号：PCT/US0124786

    申请日：2001-08-07

    Applicant: ALTERA CORP

    Inventor： METZGEN PAUL

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5045 ,  G06F17/5054

    Abstract: A hardware-to-software compiler is provided that runs an optimization on a circuit implemented in programmable logic. The optimization allows portions of the program implemented by the circuit to be executed via software. A communication interface between the hardware and software is provided that allows for efficient data flow. A communication channel is provided that can be effected as bidirectional using a unidirectional transport medium (e.g., PCI bus). Communication between devices is done through pop interface buffers and push interface buffers on either side of the communication channel.

    Abstract translation: 提供硬件到软件编译器，对可编程逻辑中实现的电路进行优化。 优化允许通过软件执行由电路实现的程序的部分。 提供硬件和软件之间的通信接口，以实现高效的数据流。 提供的通信信道可以使用单向传输介质（例如PCI总线）作为双向实现。 设备之间的通信通过弹出接口缓冲区和通信通道任一侧的接口缓冲区完成。

    SOFTWARE-TO-HARDWARE COMPILER
    3.
    发明申请
    SOFTWARE-TO-HARDWARE COMPILER 审中-公开
    软件到硬件编译器

    公开(公告)号：WO0213004A2

    公开(公告)日：2002-02-14

    申请号：PCT/US0141624

    申请日：2001-08-07

    Applicant: ALTERA CORP

    Inventor： METZGEN PAUL

    IPC: G06F17/50 ,  G06F9/00

    CPC classification number: G06F17/505 ,  G06F17/5045 ,  G06F17/5054

    Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic based on pure software constructs. More particularly, a high-level program language may be used to create a program using only software constructs that is compiled into hardware constructs. Optimizations may be made in the later stages of compilation to retime the circuit, allowing for maximum data flow. The hardware may make run-time decisions with respect to executing programmable logic blocks in parallel. The decisions may be at least partially based on a control flow.

    Abstract translation: 提供了一种基于纯软件结构的可编程逻辑生成硬件结构的软件到硬件编译器。 更具体地，可以使用高级程序语言来创建仅使用被编译成硬件结构的软件结构的程序。 可以在编译的后期进行优化，以重新加电，允许最大数据流。 硬件可以对并行执行可编程逻辑块做出运行时决定。 决定可以至少部分地基于控制流程。

    Multiplier-accumulator block mode splitting
    8.
    发明专利
    Multiplier-accumulator block mode splitting 有权
    MULTIPLIER-ACCUMULATOR BLOCK MODE SPLITTING

    公开(公告)号：JP2005235004A

    公开(公告)日：2005-09-02

    申请号：JP2004045202

    申请日：2004-02-20

    Applicant: Altera Corp ,  アルテラ・コーポレーション

    Inventor： ZHENG LEON ,  LANGHAMMER MARTIN ,  PERRY STEVEN ,  METZGEN PAUL ,  STARR GREGORY ,  HWANG WILLIAM ,  THARMALINGAM KUMARA

    IPC: G06F7/53 ,  G06F7/52 ,  G06F7/523

    Abstract: PROBLEM TO BE SOLVED: To more efficiently use a multiplier in a multiplier-accumulator (MAK) block, more concretely, a MAC block. SOLUTION: A programmable logic device includes a MAC block having mode splitting capabilities. Different operation modes can be simultaneously executed, so that multipliers and other DSP circuitry of the MAC block can be allocated among the different operation modes. For example, one multiplier may be used to execute a multiplication mode while another two multipliers may be used in two multiplication modes to execute summing. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为了在乘法器累加器（MAK）块中更有效地使用乘法器，更具体地，使用MAC块。 解决方案：可编程逻辑器件包括具有模式分离能力的MAC块。 可以同时执行不同的操作模式，从而可以在不同的操作模式之间分配MAC块的乘法器和其他DSP电路。 例如，可以使用一个乘法器来执行乘法模式，而可以在两个乘法模式中使用另外两个乘法器来执行求和。 版权所有（C）2005，JPO＆NCIPI

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