公开(公告)号：JP2000138578A

公开(公告)日：2000-05-16

申请号：JP14619499

申请日：1999-05-26

Applicant: ANALOG DEVICES INC

Inventor： SINGH JASPREET ,  KOKER GREGORY T ,  NEWMAN MARK R

IPC: H03K17/10 ,  G06F13/40 ,  H03K19/003 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide an input-output driver circuit which has both a high voltage withstand property and extensibility and which needs only two power supply pins. SOLUTION: The power supply pins required for an input-output circuit are only two pins 38 and 42 while a high voltage withstand property and extensibility are achieved by providing a buffer interface between a functional digital circuit and a common bus for another digital circuit by using two PMOS switching transistors T1A and T1B instead of one PMOS switching transistor between the output line 30 of the circuit and an output power terminal 42. For turning off the transistors T1A and T1B, the voltage of an output power source 40 is applied to the gate of one transistor T1A or T1B and the voltage at the output line 30 is applied to the gate of the other transistor T1B or T1A. Consequently, at least one of the transistors T1A and T1B can be surely turned off as required regardlessly whether or not the voltage at the output line 30 exceeds the voltage level at the output power terminal 42.

公开(公告)号：JP2002141793A

公开(公告)日：2002-05-17

申请号：JP2001270596

申请日：2001-09-06

Applicant: ANALOG DEVICES INC

Inventor： SINGH JASPREET ,  KOKER GREGORY T ,  NEWMAN MARK R

IPC: H03K17/10 ,  G06F13/40 ,  H03K19/003 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide an input output driver circuit that has both high level voltage tolerance and extensibility and has only two power supply pins. SOLUTION: The input output driver circuit employs two PMOS switching transistors (T1A, T1B) between an output line (30) of the circuit and an output power terminal (42) instead of one transistor to provide a buffer interface between a functional digital circuit (14) and a common bus (18) for other digital circuits and uses only the two required power pins (38, 42) while attaining high level voltage tolerance and the extensibility. Applying a voltage of an output power supply (40) to one-side gates of the transistors and the output line voltage to the other gates switches off the transistors. Thus, at least either of the transistors is surely turned off as required at maximum independently of whether or not the output line voltage exceeds the output power level.

公开(公告)号：DE69934048T2

公开(公告)日：2007-05-10

申请号：DE69934048

申请日：1999-05-17

Applicant: ANALOG DEVICES INC

Inventor： SINGH JASPREET ,  KOKER GREGORY T ,  NEWMAN MARK R

IPC: G06F13/40 ,  H03K17/10 ,  H03K19/003 ,  H03K19/0175

Abstract: An input/output driver circuit which provides a buffer interface between a functional digital circuit (14) and a common bus (18) for other digital circuits achieves high levels of voltage tolerance and compliance, while requiring only two power supply pins (38,42), by using two PMOS switching transistors (T1A,T1B) between the circuit's output line (30) and an output power supply terminal(42), rather than only one. To turn the transistors OFF, the output power supply (40) voltage is applied to the gate of one of them and the output line voltage to the gate of the other. This assures that at least one of the transistors is fully OFF when desired, whether or not the output line voltage exceeds the output power supply level.

公开(公告)号：DE69129074D1

公开(公告)日：1998-04-16

申请号：DE69129074

申请日：1991-06-28

Applicant: ANALOG DEVICES INC

Inventor： KOKER GREGORY T ,  TSANG STEVEN T

IPC: G06F1/06 ,  G06F1/10 ,  H03D13/00 ,  H03K5/13 ,  H03K5/26 ,  H03L7/00 ,  H03L7/081 ,  H03L7/085 ,  H03L7/089

Abstract: The invention relates to a multiple delay line comprising a multiple segment delay line (16) comprising a plurality of delay components (20-50) connected in cascade, each of said delay components producing a respective delay signal (NTAP), wherein said multiple segment delay line receives a periodic signals (PHI1) for delay thereof and wherein the delay provided by each of said delay components is determined by a first control signal (V ref ). A first phase detector receives the periodic signals PHI1) and a plurality of signals (TAP2, TAP9, TAP14) each produced by a different delay component, for determining whether there is any phase error between the produced delayed signals (TAP2, TAP9, TAP14) and the periodic signal (PHI1), and produces at least one second control signal (PD, CD, NPU, NCU) indicative of said phase error. Control signal generating means (18) is provided, responsive to at least one second control signal (PD, CD, NPU, NCU), for producing the first control signal (V ref ). First signal processing means (64, 66, 68, 70) is provided, responsive to signals (A, B, C) produced by a plurality of said delay components, for producing at least one output signal (D, E, F, G) that is a sub-phase of the periodic signal (PHI1).

公开(公告)号：DE69934048D1

公开(公告)日：2007-01-04

申请号：DE69934048

申请日：1999-05-17

Applicant: ANALOG DEVICES INC

Inventor： SINGH JASPREET ,  KOKER GREGORY T ,  NEWMAN MARK R

IPC: G06F13/40 ,  H03K17/10 ,  H03K19/003 ,  H03K19/0175

Abstract: An input/output driver circuit which provides a buffer interface between a functional digital circuit (14) and a common bus (18) for other digital circuits achieves high levels of voltage tolerance and compliance, while requiring only two power supply pins (38,42), by using two PMOS switching transistors (T1A,T1B) between the circuit's output line (30) and an output power supply terminal(42), rather than only one. To turn the transistors OFF, the output power supply (40) voltage is applied to the gate of one of them and the output line voltage to the gate of the other. This assures that at least one of the transistors is fully OFF when desired, whether or not the output line voltage exceeds the output power supply level.

公开(公告)号：DE69129074T2

公开(公告)日：1998-07-02

申请号：DE69129074

申请日：1991-06-28

Applicant: ANALOG DEVICES INC

Inventor： KOKER GREGORY T ,  TSANG STEVEN T

IPC: G06F1/06 ,  G06F1/10 ,  H03D13/00 ,  H03K5/13 ,  H03K5/26 ,  H03L7/00 ,  H03L7/081 ,  H03L7/085 ,  H03L7/089

Abstract: The invention relates to a multiple delay line comprising a multiple segment delay line (16) comprising a plurality of delay components (20-50) connected in cascade, each of said delay components producing a respective delay signal (NTAP), wherein said multiple segment delay line receives a periodic signals (PHI1) for delay thereof and wherein the delay provided by each of said delay components is determined by a first control signal (V ref ). A first phase detector receives the periodic signals PHI1) and a plurality of signals (TAP2, TAP9, TAP14) each produced by a different delay component, for determining whether there is any phase error between the produced delayed signals (TAP2, TAP9, TAP14) and the periodic signal (PHI1), and produces at least one second control signal (PD, CD, NPU, NCU) indicative of said phase error. Control signal generating means (18) is provided, responsive to at least one second control signal (PD, CD, NPU, NCU), for producing the first control signal (V ref ). First signal processing means (64, 66, 68, 70) is provided, responsive to signals (A, B, C) produced by a plurality of said delay components, for producing at least one output signal (D, E, F, G) that is a sub-phase of the periodic signal (PHI1).

公开(公告)号：DE69130486T2

公开(公告)日：1999-07-15

申请号：DE69130486

申请日：1991-06-28

Applicant: ANALOG DEVICES INC

Inventor： KOKER GREGORY T ,  TSANG STEVEN T

IPC: G06F1/06 ,  G06F1/10 ,  H03D13/00 ,  H03K5/13 ,  H03K5/26 ,  H03L7/00 ,  H03L7/081 ,  H03L7/085 ,  H03L7/089 ,  H03K5/15

Abstract: The invention relates to a multiple delay line comprising a multiple segment delay line (16) comprising a plurality of delay components (20-50) connected in cascade, each of said delay components producing a respective delay signal (NTAP), wherein said multiple segment delay line receives a periodic signals (PHI1) for delay thereof and wherein the delay provided by each of said delay components is determined by a first control signal (V ref ). A first phase detector receives the periodic signals PHI1) and a plurality of signals (TAP2, TAP9, TAP14) each produced by a different delay component, for determining whether there is any phase error between the produced delayed signals (TAP2, TAP9, TAP14) and the periodic signal (PHI1), and produces at least one second control signal (PD, CD, NPU, NCU) indicative of said phase error. Control signal generating means (18) is provided, responsive to at least one second control signal (PD, CD, NPU, NCU), for producing the first control signal (V ref ). First signal processing means (64, 66, 68, 70) is provided, responsive to signals (A, B, C) produced by a plurality of said delay components, for producing at least one output signal (D, E, F, G) that is a sub-phase of the periodic signal (PHI1).

公开(公告)号：DE69130486D1

公开(公告)日：1998-12-17

申请号：DE69130486

申请日：1991-06-28

Applicant: ANALOG DEVICES INC

Inventor： KOKER GREGORY T ,  TSANG STEVEN T

IPC: G06F1/06 ,  G06F1/10 ,  H03D13/00 ,  H03K5/13 ,  H03K5/26 ,  H03L7/00 ,  H03L7/081 ,  H03L7/085 ,  H03L7/089 ,  H03K5/15

Abstract: The invention relates to a multiple delay line comprising a multiple segment delay line (16) comprising a plurality of delay components (20-50) connected in cascade, each of said delay components producing a respective delay signal (NTAP), wherein said multiple segment delay line receives a periodic signals (PHI1) for delay thereof and wherein the delay provided by each of said delay components is determined by a first control signal (V ref ). A first phase detector receives the periodic signals PHI1) and a plurality of signals (TAP2, TAP9, TAP14) each produced by a different delay component, for determining whether there is any phase error between the produced delayed signals (TAP2, TAP9, TAP14) and the periodic signal (PHI1), and produces at least one second control signal (PD, CD, NPU, NCU) indicative of said phase error. Control signal generating means (18) is provided, responsive to at least one second control signal (PD, CD, NPU, NCU), for producing the first control signal (V ref ). First signal processing means (64, 66, 68, 70) is provided, responsive to signals (A, B, C) produced by a plurality of said delay components, for producing at least one output signal (D, E, F, G) that is a sub-phase of the periodic signal (PHI1).

公开(公告)号：WO9200558A3

公开(公告)日：1992-04-02

申请号：PCT/US9104648

申请日：1991-06-28

Applicant: ANALOG DEVICES INC

Inventor： KOKER GREGORY T ,  TSANG STEVEN T

IPC: G06F1/06 ,  G06F1/10 ,  H03D13/00 ,  H03K5/13 ,  H03K5/26 ,  H03L7/00 ,  H03L7/081 ,  H03L7/085 ,  H03L7/089 ,  G06F1/04

CPC classification number: G06F1/10 ,  G06F1/06 ,  H03D13/004 ,  H03K5/13 ,  H03K5/26 ,  H03L7/0812 ,  H03L7/0895 ,  H03L7/0896

Abstract: A phase detector (72), including multiple edge detectors (144, 146, 148), is provided for correction of any phase or frequency errors of a synchronous delay line clock generator (10). The edged detectors (144, 146, 148) provide an override of any corrective action by the rest of the phase detector to the synchronous delay line output, notwithstanding any phase error of less than 360°, if the phase position of the delay line output signal is off by an integral multiple of 360°. Taps (TAP 2, TAP 9, TAP 14) from daisy-chained or series-connected delay line elements (20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50) are provided to the phase detector (72). Each edge detector (144, 146, 148) compares the edge produced by a respective such tap against either one division of a divided clock signal or else the result of a previous such comparison. Apparatus and method are provided for saving a control signal for a signal-controlled system. The control signal is provided to a multiplexer (190), which normally outputs that control signal. That output is digitized and stored by a storage device (192) which produces a corresponding analog signal (VRLAD) as the other input to that multiplexer (190). A comparator (200) receives and compares the multiplexer (190) output and the analog signal (VRLAD). The comparator (200) thereby produces a signal (UP) to increment or decrement the stored signal.

公开(公告)号：EP3172581A4

公开(公告)日：2018-04-18

申请号：EP15825236

申请日：2015-07-25

Applicant: ANALOG DEVICES INC

Inventor： DELIWALA SHRENIK ,  DECKER STEVEN J ,  KOKER GREGORY T ,  WEINBERG DAN M

IPC: G01R19/25 ,  G01J1/44

CPC classification number: G01R15/09 ,  A61B5/02427 ,  G01J1/44 ,  G01J2001/446 ,  G01R15/08 ,  G01R19/25

Abstract: A current detection module capable of differentiating and quantifying contribution to a current signal generated by a sensor in response to stimulation by a certain target source from contributions from sources other than the target source (ambient sources) is disclosed. As long as the contribution from the target source comprises a pulsed signal, the module may synchronize itself to the pulse(s) so that there is a predetermined phase relationship between the pulse(s) and functions carried out by various stages of the module. The module may be re-used to also detect and quantify contributions from ambient sources by presenting these contributions to the module as pulses that trigger synchronization of the module. To that end, a detection system disclosed herein is based on the use of such current detection module and allows mode switching where, depending on the selected mode of operation, the module is configured to perform different measurements.