公开(公告)号：JPH03148697A

公开(公告)日：1991-06-25

申请号：JP21053990

申请日：1990-08-10

Applicant: APPLE COMPUTER

Inventor： BURAIAN DEI HAWAADO ,  ROBAATO ERU BEIRII

IPC: G06F3/153 ,  G06F15/78 ,  G09G1/16 ,  G09G1/28 ,  G09G5/00 ,  G09G5/12 ,  G09G5/18 ,  G09G5/36

Abstract: PURPOSE: To use various monitors by providing a programmable video circuit for transferring video data from a RAM to the monitor so as to supply video timing signals to the monitor and displaying the video data on the monitor. CONSTITUTION: Under the control of a CPU 13, a memory decoding unit MDU 12 receives video request signals from an RBV 14 and sends RAM control signals to the RAM 11. The RAM 11 sends the stored video data to the RBV 14. The RBV 14 receives frequencies A-C from the frequency sources 18-20 of the three different frequencies A-C and sends timing signals to the montior 27. Also, the RBV 14 supplies the video data through a bus 29 to a video A/D converter(VADC) 26. The VDAC 26 receives dot clock signals, composite blanking period signals and composite video synchronizing signals through signal lines 30, 31 and 33 and sends the color signals of RGB to the monitor 27. The monitor 27 displays images and sends monitor identification signals to the RBV 14.

公开(公告)号：JPH03130798A

公开(公告)日：1991-06-04

申请号：JP21053890

申请日：1990-08-10

Applicant: APPLE COMPUTER

Inventor： ROBAATO ERU BEIRII ,  BURAIAN DEI HAWAADO

IPC: G06F13/18 ,  G06F3/153 ,  G09G1/16 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39

Abstract: PURPOSE: To improve system performance by determining the priority of access to a RAM and refusing the access from a CPU to the RAM during the read of video data from the RAM. CONSTITUTION: A CPU 13 of a system 10 executes a program for supplying the video data to a monitor 27. The monitor 27 is programmed as a matrix composed of plural pixels. Then, the pixels are expressed by a certain number of bits in the video data stored inside the system memory or a RAM 11 of the computer. Besides, a video integrated circuit is connected to the RAM 11 and supplies the video data for N bits per pixel to the monitor 27. In this case, the priority of access to the RAM 11 is determined so as to reduce the access from the CPU 13 to the RAM 11 by a memory controller while a video circuit reads data from the RAM 11. Thus, the need of communication with a video card is eliminated to improve system performance.