公开(公告)号：JPH06318189A

公开(公告)日：1994-11-15

申请号：JP13237093

申请日：1993-05-12

Applicant: APPLE COMPUTER

Inventor： ERITSUKU SHII ANDAASON

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F15/17 ,  G06F15/177

Abstract: PURPOSE: To synchronize the frame of one or plural slave processors with the frame of a master processor and to synchronize an input data sample with an output data sample by realizing a phase register. CONSTITUTION: A processor 400 is constituted of a digital signal processor 410, and DSP 410 is driven by a DSP clock 411. A processing system 401 is connected to a sound signal DMA circuit 401 and the DMA circuit 401 facilitates the transfer of information with at least either a local memory 412 or a bus 450. A bus controller 440 connected to DSP 410 and a bus interface circuit 403 facilitating communication between a processor 401 and the bus 450 are provided furthermore. The bus 450 can be set to a computer bus to which the processor 404 can be connected or a host bus connected to the host processor 460.