公开(公告)号：JPH06217277A

公开(公告)日：1994-08-05

申请号：JP35960791

申请日：1991-12-27

Applicant: APPLE COMPUTER

Inventor： KIIICHIYAN CHIYU ,  JIEIMUZU ORIBAA NOOMAIRU ,  CHIYA RUN II ,  DANIERU UIRIAMU RAITO

IPC: G09G5/36 ,  G06T9/00 ,  H03M7/42 ,  H04N7/26 ,  H04N7/30 ,  H04N7/46 ,  H04N7/50 ,  H04N7/54 ,  H04N7/133 ,  G06F15/66

Abstract: PURPOSE: To provide an inexpensive means for decoding the data of a variable length in real time and a further efficient solving method for performing the decoding of the variable length in real time. CONSTITUTION: These method and device for decoding the code word (VLC) of the variable length by reading the VLC are provided. The VLC is provided with the maximum length of X bits. The VLC is used as an index to a first table, and in this case, the first table is provided with a value decoded for all the possible VLCs provided with Y bits not equal to any of the values of a first set. The Y is typically smaller than X and it is composed of the extremely important bit of the VLC in a preferable execution example. In the case that the first Y pieces of the bits of the VLC are not equal to any of the values of the first set, a second value is returned from the first table. In the case that the first Y pieces of the bits of the VLC are equal to one of the values of the first set, a pointer to a second table is returned from the first table.

公开(公告)号：JPH0630442A

公开(公告)日：1994-02-04

申请号：JP11429992

申请日：1992-04-08

Applicant: APPLE COMPUTER

Inventor： JIEIMUZU ORIBAA NOOMAIRU ,  CHIA RUN II ,  DANIERU UIRIAMU RAITO ,  KIICHIYAN CHIYU

IPC: H04N11/00 ,  G06T9/00 ,  H04N5/783 ,  H04N5/85 ,  H04N7/26 ,  H04N7/36 ,  H04N7/50 ,  H04N7/54 ,  H04N9/804 ,  H04N11/24 ,  H04N21/236 ,  H04N21/434

Abstract: PURPOSE: To release compression and to display a video picture with compressed movement on a real time basis by providing a plurality of calculation modules connected in parallel and processing video data for compression/compression release. CONSTITUTION: The calculation modules 401-404 of an architecture 400 have processors, dual port memories, scratch pad memories and arbitration mechanisms. A first bus 412 connects the calculation modules with a host processor 410. The processor 410 is connected to a computer system having a display device 428, a memory and other peripheral equipments. The first bus 412 is a control bus operating at relatively slow speed. A device is provided with a common memory 405 connected to the processor 410 and the modules 401-404 by a second bus 420. The bus 420 is known as a video bus and it operates at considerably faster speed than the control bus.