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公开(公告)号:JPH05233458A
公开(公告)日:1993-09-10
申请号:JP25763292
申请日:1992-09-02
Applicant: APPLE COMPUTER
Inventor: ROBAATO BUI UERANDO
Abstract: PURPOSE: To provide a memory managing unit (MMU) controlling the right of CPU to access a memory for starting the execution of operation. CONSTITUTION: MMU includes a translator translating a virtual address issued by CPU 202 to a physical address, a domain number and permission, and an environmental controller judging whether a part of a memory corresponding to the domain number can be accessed by CPU 202. The translator includes a translation index buffer(TLB) 220 and TLB generates the physical address, the domain number and permission when one entry in the translation table coincides with the page number components of the virtual address. The translator includes a translation table look up logic supplying entry information for the translation table of TLB by finding out coincidence concerning the page number components, in the memory when coincidence can not be found by TLB. In addition the translator includes a permission control logic which evaluates permission to stop the operation or to continue execution.
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公开(公告)号:JPH0635726A
公开(公告)日:1994-02-10
申请号:JP14259693
申请日:1993-05-24
Applicant: APPLE COMPUTER
Inventor: ROBAATO BUI UERANDO , UORUTAA AARU SUMISU
Abstract: PURPOSE: To eliminate the occurrence of a lock out by maintaining a data structure containing plural tasks which can be executed, giving the relevance of priority to the tasks and selecting at random tasks which are weighted by priority. CONSTITUTION: CPU 10 controls an input device 12 and an output device 14 with an instruction taken out from a memory 14, and operates data of the memory 14. An operating system has data structure with a pair of instructions controlling the operation of a computer system and it executes the selected user task. A probability priority base scheduler as a part for selecting the task in the operating system selects the task based on random numbers weighted by priority. Every task has selected finite probability which is not zero and the probability is proportional to the priority of the task. The task of low priority has a chance to be selected and lock out is executed.
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公开(公告)号:JPH05233425A
公开(公告)日:1993-09-10
申请号:JP25763192
申请日:1992-09-02
Applicant: APPLE COMPUTER
Inventor: ROBAATO BUI UERANDO
Abstract: PURPOSE: To simplify and optimize the processing and performance of address- oriented operation in an object-oriented computer. CONSTITUTION: A translator includes an address conversion unit (ATU) 436, a data conversion unit (DTL) 426, a conversion table look up logic (TTLL) 446 and a permission control logic 456. ATU generates a physical address, ADN and permission from a virtual address. When data specified and tagged by CPU 402 is a pointer, DTU generates the data main number (DDN) of the data. TTLL 446 supplies entry information for ATU and DTU. The permission control logic 456 examines permission to stop operation or to permit its continuity. MMU is provided with a cross domain control logic evaluating ADN and DDN to detect the tried flow of information characteristic to a domain. The cross domain control logic is provided with ability prohibiting the flow of information between domains and flow of control by means of CPU between the domains.
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公开(公告)号:JPH05210568A
公开(公告)日:1993-08-20
申请号:JP25763392
申请日:1992-09-02
Applicant: APPLE COMPUTER
Inventor: ROBAATO BUI UERANDO
Abstract: PURPOSE: To obtain a memory manager for the operating system of a computer device in which the usage of plural address-oriented services for the task of the operating system is supported. CONSTITUTION: Only one address space is provided to an overall system, an unique address-oriented service is related with the set of an address which is not overlapped, the service is partially attained by deciding the set of the address within the address space whose management by the service is permitted. Thus, the unique service can be prevented from managing the same address in a way the address collides against each other. Moreover in detail, a memory manager includes plural domains 112-116 (indicating the address set which is not adjacent in the address space) combined with the address-oriented services, and plural environments.
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