公开(公告)号：WO1995008800A1

公开(公告)日：1995-03-30

申请号：PCT/US1994010038

申请日：1994-09-08

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  FITCH, Jonathan

IPC: G06F09/318

CPC classification number: G06F9/3017

Abstract: An apparatus for emulation routine control transfer creates a jump host instruction (JHI) containing the address of a next emulation routine during the execution of a current emulation routine and outputs the JHI at the end of current emulation routine for transfer of host processor control. The apparatus preferably comprises: an emulated program counter (EPC), a summing means, a state machine, a pointer storage means, an opcode storage means, and a jump instruction circuit. The state machine is preferably coupled to control the loading of the EPC, the loading of the opcode storage means, the summing means, the pointer storage means and the operation of the jump instruction circuit. The pointer storage means is preferably coupled between the data bus and the jump instruction circuit. The state machine preferably issues commands on the control bus and directly to the summing means and the jump instruction circuit to prefetch the next emulation routine, create a jump instruction to the beginning of the next emulation routine and assert the jump instruction on the bus at the appropriate time to transfer directly from one emulation routine to the next using the single host jump instruction. The jump host instruction is placed upon the host processor's instruction bus after execution of the final instruction within a current emulation routine. Thus, the execution of the next emulation routine begins immediately after the execution of the jump host instruction, and significant amounts of processing time associated with the dispatch loop are eliminated.

Abstract translation: 用于仿真例程控制传输的装置在执行当前仿真程序期间产生包含下一个仿真程序的地址的跳转主机指令（JHI），并在当前仿真程序结束时输出JHI以传送主处理器控制。 该装置优选地包括：仿真程序计数器（EPC），求和装置，状态机，指针存储装置，操作码存储装置和跳转指令电路。 状态机优选地被耦合以控制EPC的加载，操作码存储装置的加载，求和装置，指针存储装置和跳转指令电路的操作。 指针存储装置优选地耦合在数据总线和跳转指令电路之间。 状态机优选地在控制总线上发出命令，并且直接向求和装置和跳转指令电路预取下一个仿真程序，创建到下一个仿真程序开始的跳转指令，并在该总线上断言跳转指令 使用单个主机跳转指令的适当时间直接从一个仿真程序传输到下一个仿真程序。 在当前仿真程序中执行最终指令之后，跳转主机指令被置于主机处理器的指令总线上。 因此，下一个仿真程序的执行在执行跳转主机指令之后立即开始，并且消除与调度循环相关联的大量处理时间。

公开(公告)号：WO1995009393A1

公开(公告)日：1995-04-06

申请号：PCT/US1994010492

申请日：1994-09-16

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  FITCH, Jonathan

IPC: G06F09/318

CPC classification number: G06F9/3017

Abstract: An apparatus for emulation routine instruction issue comprises a bus signal router, a state machine, a virtual program counter (VPC) circuit, an emulated program counter (EPC), a summing means, an opcode storage means, and a pointer storage means. The VPC circuit maintains the VPC value under the direction of the state machine. In response to a next instruction request issued by the central processing unit (CPU), the state machine outputs the VPC value to an instruction address bus, thereby causing the host instruction stored at the address indicated by the VPC to be transferred to the instruction bus and therefore be issued to the CPU. After a next host instruction request, the state machine updates the VPC value. Concurrent with the execution of the current emulation routine, the apparatus of the present invention prefetches the nest emulation routine pointer (NERP). To accomplish the NERP prefetch, the state machine issues DMA commands and commands to the EPC, the opcode storage means, and the pointer storage means. If the final host instruction in the current emulation routine has been reached, the state machine assigns the NERP to the VPC and then outputs the VPC to the instruction address bus. The method of the present invention preferably comprises the steps of: determining if a next host instruction request has been made by the CPU; outputting the VPC to the instruction address bus; and updating the VPC; and prefetching the NERP concurrent with the execution of the host instructions in the current emulation routine.

Abstract translation: 用于仿真例程指令的装置包括总线信号路由器，状态机，虚拟程序计数器（VPC）电路，仿真程序计数器（EPC），求和装置，操作码存储装置和指针存储装置。 VPC电路在状态机的方向下维持VPC值。 响应于由中央处理单元（CPU）发出的下一个指令请求，状态机将VPC值输出到指令地址总线，从而使存储在由VPC指示的地址存储的主机指令传送到指令总线 因此被发给CPU。 在下一个主机指令请求之后，状态机更新VPC值。 与当前仿真程序的执行同时，本发明的装置预取嵌套仿真例程指针（NERP）。 为了完成NERP预取，状态机向EPC，操作码存储装置和指针存储装置发出DMA命令和命令。 如果当前仿真程序中的最终主机指令已经到达，则状态机将NERP分配给VPC，然后将VPC输出到指令地址总线。 本发明的方法优选地包括以下步骤：确定CPU是否已经做出下一个主机指令请求; 将VPC输出到指令地址总线; 并更新VPC; 并且在当前仿真程序中与主机指令的执行同时预取NERP。

公开(公告)号：WO1995008799A1

公开(公告)日：1995-03-30

申请号：PCT/US1994009905

申请日：1994-09-06

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  FITCH, Jonathan

IPC: G06F09/318

CPC classification number: G06F9/3017

Abstract: An apparatus for emulation routine pointer prefetch comprises an emulated program counter (EPC), a summing means, a prefetch state machine, an opcode storage means, and a pointer storage means. The EPC, opcode storage means, and a pointer storage means are coupled to a bus to receive, store and output an emulated program counter value, an opcode value and a pointer to a next emulation routine, respectively. The EPC, opcode storage means, and pointer storage means are controlled by the prefetch state machine. The prefetch state machine is coupled to the bus to detect a reference to a reserved memory address and stores an updated emulated program counter value in the EPC using the summing means. The prefetch state machine uses the emulated program counter value to prefetch the next source instruction to be emulated in a first memory operation. A portion of the prefetched source instruction is the opcode value and is stored in the opcode storage means. The prefetch state machine uses the opcode value in a second memory operation to retrieve a pointer to a corresponding emulation routine. The pointer is stored in the pointer storage means. The method for emulation routine pointer prefetch preferably comprises the steps of determining if a currently executing emulation routine has issued an instruction to update the EPC; prefetching a next source instruction based upon the value of the EPC; and utilizing an opcode within the prefetched source instruction to prefetch a pointer to a next emulation routine corresponding to the prefetched source instruction.

Abstract translation: 用于仿真例程指针预取的装置包括仿真程序计数器（EPC），求和装置，预取状态机，操作码存储装置和指针存储装置。 EPC，操作码存储装置和指针存储装置耦合到总线，以分别接收，存储和输出仿真的程序计数器值，操作码值和指向下一仿真程序的指针。 EPC，操作码存储装置和指针存储装置由预取状态机控制。 预取状态机耦合到总线以检测对保留存储器地址的引用，并使用求和装置将更新的仿真程序计数器值存储在EPC中。 预取状态机使用仿真程序计数器值在第一个存储器操作中预取要仿真的下一个源指令。 预取源指令的一部分是操作码值，并存储在操作码存储装置中。 预取状态机在第二存储器操作中使用操作码值来检索指向相应仿真程序的指针。 指针存储在指针存储装置中。 用于仿真例程指针预取的方法优选地包括以下步骤：确定当前执行的仿真程序是否已经发出更新EPC的指令; 根据EPC的值预取下一个源指令; 以及利用预取源指令内的操作码预读取与预取源指令对应的下一个仿真程序的指针。

公开(公告)号：WO1995008798A1

公开(公告)日：1995-03-30

申请号：PCT/US1994009904

申请日：1994-09-06

Applicant: APPLE COMPUTER, INC.

Inventor： APPLE COMPUTER, INC. ,  FITCH, Jonathan

IPC: G06F09/318

CPC classification number: G06F12/0802 ,  G06F9/45504

Abstract: An instruction mapping system comprises an instruction mapping circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The instruction mapping circuit's address inputs are coupled to the first address bus, and the instruction mapping circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the instruction mapping circuit. The instruction mapping circuit determines whether the pointer address indicates that the next source instruction is within the subset of most frequently executed source instructions. If so, the instruction mapping circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the instruction mapping circuit unchanged. The pointer address is next routed to the data cache and to the RAM via the second address bus. If the pointer address was mapped to a data cache address, the data cache outputs the pointer to the next emulation routine on the data bus. If the pointer address was not mapped to a data cache address, the pointer to the next emulation routine is output on the data bus at the data outputs of the memory. The present invention also includes a method for manufacturing an instruction mapping system.

Abstract translation: 指令映射系统包括指令映射电路，中央处理单元（CPU），数据高速缓存和存储器。 CPU的地址输出耦合到第一地址总线，而数据高速缓存和存储器的地址输入耦合到第二地址总线。 指令映射电路的地址输入耦合到第一地址总线，并且指令映射电路的输出耦合到第二地址总线。 CPU通过第一地址总线将指针地址发送到指令映射电路。 指令映射电路确定指针地址是否指示下一个源指令在最常执行的源指令的子集内。 如果是这样，指令映射电路将指针地址映射到数据高速缓存内的地址。 如果不是，指针地址通过指令映射电路不变地被路由。 指针地址接下来通过第二个地址总线路由到数据高速缓存和RAM。 如果指针地址映射到数据高速缓存地址，则数据高速缓存将指针指向数据总线上的下一个仿真程序。 如果指针地址未映射到数据高速缓存地址，则在存储器的数据输出处，在数据总线上输出指向下一个仿真程序的指针。 本发明还包括用于制造指令映射系统的方法。