公开(公告)号：NL2007481C

公开(公告)日：2012-11-13

申请号：NL2007481

申请日：2011-09-27

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  MACHNICKI ERIC P ,  BALKAN DENIZ ,  GUPTA VIJAY

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0802 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

公开(公告)号：GB2484204B

公开(公告)日：2013-02-13

申请号：GB201116886

申请日：2011-09-30

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  MACHNICKI ERIK P ,  BALKAN DENIZ ,  GUPTA VIJAY

IPC: G06F1/32 ,  G06F9/44 ,  G06F12/08

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

公开(公告)号：NL2007481A

公开(公告)日：2012-04-02

申请号：NL2007481

申请日：2011-09-27

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  MACHNICKI ERIC P ,  BALKAN DENIZ ,  GUPTA VIJAY

IPC: G06F1/32

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

公开(公告)号：NL2007481C2

公开(公告)日：2012-11-13

申请号：NL2007481

申请日：2011-09-27

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  MACHNICKI ERIC P ,  BALKAN DENIZ ,  GUPTA VIJAY

IPC: G06F1/32

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

公开(公告)号：GB2484204A

公开(公告)日：2012-04-04

申请号：GB201116886

申请日：2011-09-30

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  MACHNICKI ERIK P ,  BALKAN DENIZ ,  GUPTA VIJAY

IPC: G06F1/32 ,  G06F9/445 ,  G06F12/08

Abstract: A control circuit 30 is configured to transmit a set of operations to a circuit block 18A, which is being powered up after being powered down, in order to reinitialize the circuit block. The circuit block may be a cache coupled to one or more processors 16, and the operations may be connected to configuration registers 56A-D within the cache. The operations may be stored in a memory 60 (e.g. a set of registers) to which the control circuit is coupled. The control circuit is also configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. This allows the circuit block to be powered up or powered down during times that the processors in the system are powered down (and thus software is not executable at the time), without requiring the waking of the processors for the power up/power down event, and therefore conserving power.