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公开(公告)号：KR20180032626A
公开(公告)日：2018-03-30
申请号：KR20187005237
申请日：2016-06-09
Applicant: APPLE INC
Inventor： MILLET TIMOTHY J , GULATI MANU , SPENCE ARTHUR L , SAUND GURJEET S , ESSER ROBERT P
CPC classification number: G06T1/20 , G06F9/4893 , G06F9/52 , G06T1/60 , G09G5/001 , G09G5/363 , Y02B60/144 , Y02D10/24
Abstract: 시스템의일 실시예는복수의미디어유닛, 프로세서, 및회로부를포함할수 있다. 각각의미디어유닛은디스플레이이미지를프로세싱하기위해하나이상의커맨드를실행하도록구성될수 있다. 프로세서는큐(queue)에복수의미디어프로세싱커맨드를저장하도록구성될수 있다. 회로부는큐로부터제1 미디어프로세싱커맨드를검색하고제1 미디어프로세싱커맨드를제1 미디어유닛에전송하도록구성될수 있다. 회로부는또한큐로부터제2 미디어프로세싱을검색하고제1 미디어유닛으로부터인터럽트(interrupt)를수신하는것에응답하여제2 미디어프로세싱커맨드를제2 미디어유닛에전송하도록구성될수 있다. 이어서, 회로부는제1 미디어유닛으로부터인터럽트를수신하는것에응답하여제1 미디어유닛으로부터제2 미디어유닛으로데이터를복사할수 있다.
Abstract translation: 该系统的一个实施例可以包括多个媒体单元，处理器和电路。 每个媒体单元可以被配置为执行一个或多个命令来处理显示图像。 处理器可以被配置为将多个媒体处理命令存储在队列中。 电路可以被配置为从队列中检索第一媒体处理命令并且将第一媒体处理命令发送到第一媒体单元。 电路单元还可以被配置为从该队列，并且响应于从所述第一媒体单元接收到中断（中断）到所述第二媒体处理命令发送到所述第二媒体单元检索所述第二媒体处理。 该电路然后可以响应于从第一媒体单元接收到中断，将数据从第一媒体单元复制到第二媒体单元。
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公开(公告)号：DE112016003527B4
公开(公告)日：2025-02-20
申请号：DE112016003527
申请日：2016-06-09
Applicant: APPLE INC
Inventor： MILLET TIMOTHY J , GULATI MANU , SPENCE ARTHUR L , SAUND GURJEET S , ESSER ROBERT P
Abstract: System, umfassend:einen Prozessor (101, 101a, 101b), eine Mehrzahl von Medieneinheiten (110, 111, 112) und einen Medienverwalter (130, 200, 301), die jeweils über einen Systembus (102, 202) gekoppelt sind,wobei jede Medieneinheit (110, 111, 112) konfiguriert ist, um einen oder mehrere Befehle auszuführen, um ein Anzeigebild zu verarbeiten;wobei der Prozessor (101, 101a, 101b) konfiguriert ist, um eine Mehrzahl von Medienverarbeitungsbefehlen in einer Warteschlange (303) zu speichern; wobei der Medienverwalter (130, 200, 301) konfiguriert ist, zum:Abrufen eines ersten Medienverarbeitungsbefehls der Mehrzahl von Medienverarbeitungsbefehlen aus der Warteschlange (303);Senden des ersten Medienverarbeitungsbefehls an eine erste Medieneinheit der Mehrzahl von Medieneinheiten (110, 111, 112);Abrufen, während der erste Medienverarbeitungsbefehl durch die erste Medieneinheit ausgeführt wird, eines zweiten Medienverarbeitungsbefehls der Mehrzahl von Medienverarbeitungsbefehlen aus der Warteschlange (303);falls der Medienverwalter (130, 200, 301) feststellt, dass der zweite Medienverarbeitungsbefehl unabhängig von einer Ausführung des ersten Medienverarbeitungsbefehls ist, Senden des zweiten Medienverarbeitungsbefehls an eine zweite Medieneinheit der Mehrzahl von Medieneinheiten (110, 111, 112), undandernfalls, in Antwort auf ein Empfangen eines Interrupts von der ersten Medieneinheit, der angibt, dass die erste Medieneinheit den ersten Medienverarbeitungsbefehl abgeschlossen hat:Senden des zweiten Medienverarbeitungsbefehl an die zweite Medieneinheit,Kopieren von Daten aus dem Speicher der ersten Medieneinheit, die durch den ersten Medienverarbeitungsbefehl erzeugt wurden, in den Speicher der zweiten Medieneinheit für eine weitere Verarbeitung.
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公开(公告)号：AU2014349165A1
公开(公告)日：2016-04-21
申请号：AU2014349165
申请日：2014-09-26
Applicant: APPLE INC
Inventor： SILVERSTEIN D AMNON , GO SHUN WAI , LIM SUK HWAN , MILLET TIMOTHY J , CHEN TING , NI BIN
Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4x3 aspect ratio and at higher resolution than the 16x9 aspect ratio video frames. The device may interleave high resolution, 4x3 frames and lower resolution 16x9 frames in the video sequence, and may capture the nearest higher resolution, 4x3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16x9 frames in the video sequence, and then expand to 4x3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16x9 video frames responsive to a release of the shutter button.
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公开(公告)号：NL2007481C2
公开(公告)日：2012-11-13
申请号：NL2007481
申请日：2011-09-27
Applicant: APPLE INC
Inventor： MILLET TIMOTHY J , MACHNICKI ERIC P , BALKAN DENIZ , GUPTA VIJAY
IPC: G06F1/32
Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.
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公开(公告)号：GB2484204A
公开(公告)日：2012-04-04
申请号：GB201116886
申请日：2011-09-30
Applicant: APPLE INC
Inventor： MILLET TIMOTHY J , MACHNICKI ERIK P , BALKAN DENIZ , GUPTA VIJAY
Abstract: A control circuit 30 is configured to transmit a set of operations to a circuit block 18A, which is being powered up after being powered down, in order to reinitialize the circuit block. The circuit block may be a cache coupled to one or more processors 16, and the operations may be connected to configuration registers 56A-D within the cache. The operations may be stored in a memory 60 (e.g. a set of registers) to which the control circuit is coupled. The control circuit is also configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. This allows the circuit block to be powered up or powered down during times that the processors in the system are powered down (and thus software is not executable at the time), without requiring the waking of the processors for the power up/power down event, and therefore conserving power.
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Patent Agency Ranking
公开(公告)号：DE112015004438T5
公开(公告)日：2017-06-29
申请号：DE112015004438
申请日：2015-08-17
Applicant: APPLE INC
Inventor： GULATI MANU , COX KEITH , MILLET TIMOTHY J , DE LA CROPTE DE CHANTERAC CYRIL , MACHNICKI ERIK P
IPC: G06F1/32
Abstract: Ausführungsformen eines Verfahrens, das die Anpassung von Leistungseinstellungen eines Computersystems ermöglicht, werden offenbart. Eine oder mehrere Funktionseinheiten können mehrere Monitorschaltungen einschließen, die jeweils konfiguriert sein können, um einen gegebenen Betriebsparameter einer dazugehörigen Funktionseinheit zu überwachen. Nach einem Erfassen eines Ereignisses in Zusammenhang mit einem überwachten Betriebsparameter kann eine Monitorschaltung einen Interrupt erzeugen. Als Reaktion auf den Interrupt kann ein Prozessor eine oder mehrere Leistungseinstellungen des Computersystems anpassen.
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公开(公告)号：BR112013003738A2
公开(公告)日：2016-05-31
申请号：BR112013003738
申请日：2011-08-11
Applicant: APPLE INC
Inventor： COTE GUY , FREDERIKSEN JEFFREY E , BRATT JOSEPH P , GO SHUN WAI , MILLET TIMOTHY J
IPC: H04N5/232
Abstract: método e sistema de processamento de imagem de sensor de imagem duplo. trata-se de várias técnicas fornecidas para processar dados de imagem adquiiridos com o uso de ums ensor de imagem digital 90. de acordo com aspctos da presente revelação, tal técnica pode se referir ao processamento de dados de imagem em um sistema 10 que suporta múltiplos sensores de imagem 90. em uma modalidade, o sistema de processamento de imagem 32 pode incluir circuitos de controle configurados para determinar se um dispositivo está operando em um modo de sensor único (um sensor ativo) ou um modo de sensor duplo (dois sensores ativos). durante a operação no modo de sensor único, os dados podem ser fornecidos diretamente para uma unidade de processamento de pixel front-end 80 da interface de sensor do sensor ativo. durante a operação em um modo de sensor duplo, os quadros de imagem do primeiro e do segundo sensores 90a, 90b são fornecidos para a unidade de processamento de pixel front-end 80 de uma forma intercalada. por exemplo, em uma modalidade, os quadros de imagem do primeiro e do segundo sensores 90, 90b são descritos para uma memória 108, e então lidos para a unidade de processamento de pixel front-end 80 de uma forma intercalada.
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公开(公告)号：AU2012227271B2
公开(公告)日：2014-10-23
申请号：AU2012227271
申请日：2012-09-21
Applicant: APPLE INC
Inventor： TRIPATHI BRIJESH , MILLET TIMOTHY J
Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface. Reference 300 Clock hardware PLL update i BB hardware 302 304 311 high speed 30 Data serial ck ck p/L_c/k interface u baseband 208 dsicfk firmware mux 312 se/ PLL state mane victim update _PLL update request . serial interface baseband drvrAdd Victims driver kernelRemoveVictims 318 (executed on processor) Fig. 2
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公开(公告)号：AU2012227271A1
公开(公告)日：2013-05-30
申请号：AU2012227271
申请日：2012-09-21
Applicant: APPLE INC
Inventor： TRIPATHI BRIJESH , MILLET TIMOTHY J
Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface. Reference 300 Clock hardware PLL update i BB hardware 302 304 311 high speed 30 Data serial ck ck p/L_c/k interface u baseband 208 dsicfk firmware mux 312 se/ PLL state mane victim update _PLL update request . serial interface baseband drvrAdd Victims driver kernelRemoveVictims 318 (executed on processor) Fig. 2
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公开(公告)号：AU2011292290A1
公开(公告)日：2013-03-07
申请号：AU2011292290
申请日：2011-08-11
Applicant: APPLE INC
Inventor： COTE GUY , FREDERIKSEN JEFFREY E , BRATT JOSEPH P , GO SHUN WAI , MILLET TIMOTHY J
IPC: H04N5/232
Abstract: Various techniques are provided for processing image data acquired using a digital image sensor 90. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system 10 that supports multiple image sensors 90. In one embodiment, the image processing system 32 may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit 80 from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors 90a, 90b are provided to the front-end pixel processing unit 80 in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors 90a, 90b are written to a memory 108, and then read out to the front-end pixel processing unit 80 in an interleaved manner.
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