公开(公告)号：GB2477417A

公开(公告)日：2011-08-03

申请号：GB201101430

申请日：2011-01-27

Applicant: APPLE INC

Inventor： IWAMOTO DEREK ,  SFARZO STEVEN J ,  SCHMIDT RYAN ,  CARTY DEREK ,  COX KEITH

IPC: G06F9/445 ,  G06F1/32 ,  G11C5/14

Abstract: A data processing system comprises a volatile memory, such as DRAM; at least one data input peripheral; and a logic circuit that is configured to manage power consumption of the data processing system during a sleep state of the system. The logic circuit is coupled to the volatile memory, and is configured to turn off power to the volatile memory in response to an event occurring during the sleep state, but to have the rest of the system remain in the sleep state. This reduces power consumption. The sleep state may be an ACPI-compliant S3 sleep state, in which the volatile memory is powered off after a period of user inactivity during the S3 state. This period may be determined by the expiration of a timer, in response to an action of the user, such as a specific key sequence or the closing of a lid, or based on a condition of the system at the time of entering the sleep state. The system may transfer the data in the volatile memory to a non-volatile memory before entering the sleep state.