公开(公告)号：AU2011332209B2

公开(公告)日：2015-01-15

申请号：AU2011332209

申请日：2011-11-14

Applicant: APPLE INC

Inventor： MACHNICKI ERIK P ,  CHEN HAO ,  MANSINGH SANJAY

IPC: H03L7/06

Abstract: An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.

公开(公告)号：AU2011332209A1

公开(公告)日：2013-05-09

申请号：AU2011332209

申请日：2011-11-14

Applicant: APPLE INC

Inventor： MACHNICKI ERIK P ,  CHEN HAO ,  MANSINGH SANJAY

IPC: H03L7/06

Abstract: An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.