公开(公告)号：WO2023033955A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/038644

申请日：2022-07-28

Applicant: APPLE INC.

Inventor： NATARAJAN, Rohit ,  SCHULZ, Jurgen M. ,  SHULER, Christopher D. ,  GUPTA, Rohit K. ,  ZOU, Thomas T. ,  SRIDHARAN, Srinivasa Rangan

IPC: G06F12/0802 ,  G06F3/06

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：WO2021025987A1

公开(公告)日：2021-02-11

申请号：PCT/US2020/044464

申请日：2020-07-27

Applicant: APPLE INC.

Inventor： KLINGAUF, Wolfgang H. ,  CHEUNG, Connie W. ,  GUPTA, Rohit K. ,  NATARAJAN, Rohit ,  HEPPOLETTE, Vanessa Cristina ,  LINGUTLA, Varaprasad V. ,  KANCHANA, Muditha

IPC: G06F12/0895 ,  G06F12/0877 ,  G06F12/0893

Abstract: Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.

公开(公告)号：WO2022055594A1

公开(公告)日：2022-03-17

申请号：PCT/US2021/039213

申请日：2021-06-25

Applicant: APPLE INC.

Inventor： RACHAKONDA, Ramana V. ,  GUPTA, Rohit K. ,  SIMERAL, Brad W. ,  HOLLAND, Peter F.

IPC: G06F1/3206 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3287

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.