公开(公告)号：WO2014035584A1

公开(公告)日：2014-03-06

申请号：PCT/US2013/052663

申请日：2013-07-30

Applicant: APPLE INC.

Inventor： MURPHY, Michael W.

IPC: G06F13/368

CPC classification number: G06F13/368 ,  G06F2213/0026

Abstract: The disclosed embodiments provide a system that facilitates use of a network of components in a computer system. The system includes a bandwidth-allocation apparatus that provides a write transaction limit for a component on the network. The system also includes a transaction-management apparatus that compares the write transaction limit to a set of outstanding write transactions for the component upon detecting a write transaction from the component to the network. If the write transaction causes the set of outstanding write transactions to exceed the write transaction limit, the transaction-management apparatus restricts transmission of the write transaction over the network.

Abstract translation: 所公开的实施例提供了便于在计算机系统中使用组件网络的系统。 该系统包括为网络上的组件提供写入事务限制的带宽分配装置。 该系统还包括事务管理装置，其在检测到从组件到网络的写入事务时将写事务限制与组件的一组未完成的写事务进行比较。 如果写入事务导致一组未完成的写入事务超过写入事务限制，则事务管理装置限制通过网络的写入事务的传输。

公开(公告)号：WO2014046847A1

公开(公告)日：2014-03-27

申请号：PCT/US2013/056668

申请日：2013-08-26

Applicant: APPLE INC.

Inventor： MURPHY, Michael W. ,  DE CESARE, Joshua P. ,  PAASKE, Timothy R.

IPC: G06F13/24 ,  G06F1/32

CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。