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    INFERRING USER INTENT FROM BATTERY USAGE LEVEL AND CHARGING PATTERN
    2.
    发明申请
    INFERRING USER INTENT FROM BATTERY USAGE LEVEL AND CHARGING PATTERN 审中-公开
    从电池使用级别和充电模式感染用户信息

    公开(公告)号：WO2014046860A1

    公开(公告)日：2014-03-27

    申请号：PCT/US2013/057376

    申请日：2013-08-29

    Applicant: APPLE INC.

    Inventor： DE CESARE, Joshua P. ,  KAPOOR, Gaurav

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/3212 ,  G06F11/3438 ,  Y02D10/174 ,  Y02D10/34

    Abstract: Techniques for power management of a portable device are described herein. According to one embodiment, a user agent of an operating system executed within a portable device is configured to monitor daily battery usage of a battery of the portable device, to capturing, by the user agent, daily battery charging pattern of the battery of the portable device, and to inferring, by the user agent, user intent of utilizing the portable device at a given point in time based on a battery operating condition at the point in time in view of the daily battery usage and the daily battery charging pattern. Power management logic is configured to perform power management actions based on the user intent.

    Abstract translation: 本文描述了用于便携式设备的电源管理的技术。 根据一个实施例，在便携式设备内执行的操作系统的用户代理被配置为监视便携式设备的电池的每日电池使用量，以便由用户代理捕获便携式设备的电池的每日电池充电模式 设备，并且由用户代理根据每日电池使用和每日电池充电模式，基于在该时间点的电池操作条件，在给定时间点推断便携式设备的用户意图。 电源管理逻辑被配置为基于用户意图执行电源管理动作。

    MULTIPLE MAILBOX SECURE CIRCUIT
    3.
    发明申请
    MULTIPLE MAILBOX SECURE CIRCUIT 审中-公开

    公开(公告)号：WO2019118203A1

    公开(公告)日：2019-06-20

    申请号：PCT/US2018/063229

    申请日：2018-11-30

    Applicant: APPLE INC.

    Inventor： BENSON, Wade ,  SMITH, Michael J. ,  DE CESARE, Joshua P.

    IPC: G06F21/72 ,  G06F21/74 ,  G06F15/167 ,  G06F12/14

    Abstract: Techniques are disclosed relating to data storage. In various embodiments, a computing device includes first and second processors and memory having stored therein a first encrypted operating system executable by the first processor and a second encrypted operating system executable by the second processor. The computing device also includes a secure circuit configured to receive, via a first mailbox mechanism of the secure circuit, a first request from the first processor for a first cryptographic key usable to decrypt the first operating system. The secure circuit is further configured to receive, via a second mailbox mechanism of the secure circuit, a second request from the second processor for a second cryptographic key usable to decrypt the second operating system, and to provide the first and second cryptographic keys.

    PREDICTING USER INTENT AND FUTURE INTERACTION FROM APPLICATION ACTIVITIES
    6.
    发明申请
    PREDICTING USER INTENT AND FUTURE INTERACTION FROM APPLICATION ACTIVITIES 审中-公开
    预测用户的意图和未来的应用活动的相互作用

    公开(公告)号：WO2014046862A1

    公开(公告)日：2014-03-27

    申请号：PCT/US2013/057388

    申请日：2013-08-29

    Applicant: APPLE INC.

    Inventor： DE CESARE, Joshua P. ,  KAPOOR, Gaurav ,  ANDREWS, Jonathan J.

    IPC: G06F1/32

    CPC classification number: G06F1/3206

    Abstract: Techniques for power management of a portable device are described herein. According to one embodiment, a user agent of an operating system executed within a portable device is configured to monitor activities of programs running within the portable device and to predict user intent at a given point in time and possible subsequent user interaction with the portable device based on the activities of the program. Power management logic is configured to adjust power consumption of the portable device based on the predicted user intent and subsequent user interaction of the portable device, such that remaining power capacity of a battery of the portable device satisfies intended usage of the portable device.

    Abstract translation: 本文描述了用于便携式设备的电源管理的技术。 根据一个实施例，在便携式设备内执行的操作系统的用户代理被配置为监视在便携式设备内运行的程序的活动并且在给定时间点预测用户意图以及可能的后续用户与便携式设备的交互 关于方案的活动。 电源管理逻辑被配置为基于便携式设备的预测用户意图和随后的用户交互来调整便携式设备的功耗，使得便携式设备的电池的剩余电力容量满足便携式设备的预期使用。

    TIMESTAMP BASED DISPLAY UPDATE MECHANISM
    7.
    发明申请
    TIMESTAMP BASED DISPLAY UPDATE MECHANISM 审中-公开
    基于TIMESTAMP的显示更新机制

    公开(公告)号：WO2017058343A1

    公开(公告)日：2017-04-06

    申请号：PCT/US2016/043394

    申请日：2016-07-21

    Applicant: APPLE INC.

    Inventor： TRIPATHI, Brijesh ,  SPENCE, Arthur L. ,  DE CESARE, Joshua P. ,  GARBACEA, Ilie ,  COTE, Guy ,  CHAPPALLI, Mahesh B. ,  GRAY, Malcolm D. ,  TANN, Christopher P.

    IPC: G06F3/147 ,  G06F3/14

    CPC classification number: G09G5/395 ,  G06F3/1407 ,  G06F3/147 ,  G09G2310/08 ,  G09G2340/0407 ,  G09G2340/0464 ,  G09G2360/127

    Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals (810), the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value (815). If the timestamp is earlier than the global timer value (820), the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory (825). The display control unit may then apply the updates of the frame configuration set to its pixel processing elements (835). After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display (840).

    Abstract translation: 用于实现基于时间戳的显示更新机制的系统，装置和方法。 显示控制单元包括用于存储时间戳的时间戳队列，其中每个时间戳指示何时应当从存储器取出对应的帧配置集。 以预定义的间隔（810），显示控制单元可以将时间戳队列的最上面的条目的时间戳与全局定时器值（815）进行比较。 如果时间戳早于全局定时器值（820），则显示控制单元可以弹出时间戳条目并从存储器提取下一个配置集合（825）。 然后，显示控制单元可以将帧配置集的更新应用于其像素处理元件（835）。 在应用更新之后，显示控制单元可以获取并处理源像素数据，然后将下一帧的像素驱动到显示器（840）。

    REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK
    8.
    发明申请
    REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK 审中-公开
    在外围组件互联互通链接中减少延迟

    公开(公告)号：WO2014046847A1

    公开(公告)日：2014-03-27

    申请号：PCT/US2013/056668

    申请日：2013-08-26

    Applicant: APPLE INC.

    Inventor： MURPHY, Michael W. ,  DE CESARE, Joshua P. ,  PAASKE, Timothy R.

    IPC: G06F13/24 ,  G06F1/32

    CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

    Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

    Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。

    HARDWARE AUTOMATIC PERFORMANCE STATE TRANSITIONS IN SYSTEM ON PROCESSOR SLEEP AND WAKE EVENTS
    9.
    发明公开
    HARDWARE AUTOMATIC PERFORMANCE STATE TRANSITIONS IN SYSTEM ON PROCESSOR SLEEP AND WAKE EVENTS 审中-公开

    公开(公告)号：EP4273666A3

    公开(公告)日：2024-01-24

    申请号：EP23191129.8

    申请日：2011-04-07

    Applicant: Apple Inc.

    Inventor： DE CESARE, Joshua P. ,  CHO, Jung Wook ,  TAKAYANAGI, Toshi ,  MILLET, Timothy J.

    IPC: G06F1/32 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3287

    Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

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