公开(公告)号：WO2020112504A1

公开(公告)日：2020-06-04

申请号：PCT/US2019/062701

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： ZHONG, Chonghua ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00

Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.

公开(公告)号：WO2018226394A2

公开(公告)日：2018-12-13

申请号：PCT/US2018/033813

申请日：2018-05-22

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  ZHONG, Chonghua ,  HU, Kunzhong

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

公开(公告)号：WO2016164119A1

公开(公告)日：2016-10-13

申请号：PCT/US2016/020289

申请日：2016-03-01

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  ZHONG, Chonghua ,  PANG, Mengzhi ,  YANG, Se Young

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83

Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) (130) formed directly on a top die (110), and a bottom die (150) mounted on a back surface of the RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装包括直接形成在顶模（110）上的再分配层（RDL）（130）和安装在RDL的后表面上的底模（150）。

公开(公告)号：WO2016140819A2

公开(公告)日：2016-09-09

申请号：PCT/US2016/018804

申请日：2016-02-19

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  LAI, Kwan-Yu ,  PANG, Mengzhi ,  ZHONG, Chonghua ,  YANG, Se Young

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL）以及附接到第一RDL的前侧和后侧的多个管芯。 第一和第二RDL与从第一RDL的后侧延伸到第二RDL的前侧的多个导电柱连接在一起。

公开(公告)号：WO2020176313A1

公开(公告)日：2020-09-03

申请号：PCT/US2020/018883

申请日：2020-02-19

Applicant: APPLE INC.

Inventor： ZHONG, Chonghua ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/538

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：WO2018226394A3

公开(公告)日：2018-12-13

申请号：PCT/US2018/033813

申请日：2018-05-22

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  ZHONG, Chonghua ,  HU, Kunzhong

IPC: H01L21/60 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L21/98 ,  H01L21/683 ,  H01L25/18

Abstract: Multiple component package structures are described in which an interposer chiplet (110) is integrated to provide fine routing between components. In an embodiment, the interposer chiplet (110) and a plurality of conductive vias (142) are encapsulated in an encapsulation layer (140). A first plurality of terminals (135A) of the first (130) and second (132) components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals (135B) of first and second components may be in electrical connection with the interposer chiplet (110).

公开(公告)号：WO2016010859A1

公开(公告)日：2016-01-21

申请号：PCT/US2015/040013

申请日：2015-07-10

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  ZHONG, Chonghua

IPC: H01L25/10 ,  G11C5/02 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: In some embodiments, a semiconductor device package on package assembly may include a first package, a second package, and a third package. The first package may include a first surface, a second surface, a first die, and a first set of electrical conductors. The first set of electrical conductors may be configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface, and a local memory module. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The third package may include a fifth surface and a sixth surface, and a main memory module. The fifth surface may be coupled to the fourth surface. The third package may be electrically coupled to the first package and/or the second package.

Abstract translation: 在一些实施例中，封装组件上的半导体器件封装可以包括第一封装，第二封装和第三封装。 第一封装可以包括第一表面，第二表面，第一管芯和第一组电导体。 第一组电导体可以被配置为电连接封装组件上的封装。 第二包装可以包括第三表面和第四表面以及本地存储器模块。 第三表面可以联接到第二表面。 第一封装可以电耦合到第二封装。 第三包装可以包括第五表面和第六表面，以及主存储器模块。 第五表面可以联接到第四表面。 第三封装可以电耦合到第一封装和/或第二封装。