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    SUBSTRATE PROCESSING METHOD AND DEVICE MANUFACTURED BY THE SAME
    2.
    发明申请
    SUBSTRATE PROCESSING METHOD AND DEVICE MANUFACTURED BY THE SAME 有权

    公开(公告)号：US20210035988A1

    公开(公告)日：2021-02-04

    申请号：US17072480

    申请日：2020-10-16

    Applicant: ASM IP Holding B.V.

    Inventor： Tae Hee Yoo ,  Yoon Ki Min ,  Yong Min Yoo

    IPC: H01L27/1157 ,  H01L21/311 ,  H01L21/768 ,  H01L27/11524 ,  H01L21/02 ,  H01L27/11575 ,  H01L27/11548

    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution,

    SUBSTRATE PROCESSING METHOD AND DEVICE MANUFACTURED BY THE SAME
    4.
    发明申请
    SUBSTRATE PROCESSING METHOD AND DEVICE MANUFACTURED BY THE SAME 审中-公开

    公开(公告)号：US20180301460A1

    公开(公告)日：2018-10-18

    申请号：US15951626

    申请日：2018-04-12

    Applicant: ASM IP Holding B.V.

    Inventor： Tae Hee Yoo ,  Yoon Ki Min ,  Yong Min Yoo

    IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L21/768 ,  H01L21/311

    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in the process of selectively depositing a landing pad in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20180069019A1

    公开(公告)日：2018-03-08

    申请号：US15798150

    申请日：2017-10-30

    Applicant: ASM IP Holding B.V.

    Inventor： Young Jae Kim ,  Seung Woo Choi ,  Yong Min Yoo

    IPC: H01L27/11582 ,  H01L21/225 ,  H01L21/28

    CPC classification number: H01L27/11582 ,  H01L21/2255 ,  H01L29/40117

    Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

    Method of depositing thin film
    6.
    发明授权
    Method of depositing thin film 有权
    沉积薄膜的方法

    公开(公告)号：US09330899B2

    公开(公告)日：2016-05-03

    申请号：US14067686

    申请日：2013-10-30

    Applicant: ASM IP Holding B.V.

    Inventor： In Soo Jung ,  Eun Kee Hong ,  Seung Woo Choi ,  Dong Seok Kang ,  Yong Min Yoo ,  Pei-Chung Hsiao

    IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/311

    CPC classification number: H01L21/02126 ,  C23C16/401 ,  C23C16/45529 ,  C23C16/45536 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31111

    Abstract: A method for forming a silicon germanium oxide thin film on a substrate in a reaction space may be performed using an atomic layer deposition (ALD) process. The process may include at least one cycle comprising a germanium oxide deposition sub-cycle and a silicon oxide deposition sub-cycle. The germanium oxide deposition sub-cycle may include contacting the substrate with a germanium reactant, removing excess germanium reactant, and contacting the substrate with a first oxygen reactant. The silicon oxide deposition sub-cycle may include contacting the substrate with a silicon reactant, removing excess silicon reactant, and contacting the substrate with a second oxygen reactant. The films of the present disclosure exhibit desirable etch rates relative to thermal oxide. Depending on the films' composition, the etch rates may be higher or lower than the etch rates of thermal oxide.

    Abstract translation: 可以使用原子层沉积（ALD）工艺在反应空间中的基板上形成氧化硅氧化物薄膜的方法。 该方法可以包括至少一个包括氧化锗沉积子循环和氧化硅沉积子循环的循环。 氧化锗沉积子循环可以包括使基底与锗反应物接触，除去过量的锗反应物，并使基底与第一氧反应物接触。 氧化硅沉积子循环可以包括使衬底与硅反应物接触，除去过量的硅反应物，并使衬底与第二氧反应物接触。 本公开的膜显示出相对于热氧化物的期望的蚀刻速率。 取决于膜的组成，蚀刻速率可以高于或低于热氧化物的蚀刻速率。

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