公开(公告)号：US10137643B2

公开(公告)日：2018-11-27

申请号：US14456586

申请日：2014-08-11

Applicant: ASML NETHERLANDS B.V.

Inventor： Yu Cao ,  Wenjin Shao ,  Ronaldus Johannes Gijsbertus Goossens ,  Jun Ye ,  James Patrick Koonmen

IPC: G06F17/50 ,  B29C67/00 ,  G03F7/20

Abstract: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.

公开(公告)号：US10569469B2

公开(公告)日：2020-02-25

申请号：US14525704

申请日：2014-10-28

Applicant: ASML NETHERLANDS B.V.

Inventor： Yu Cao ,  Wenjin Shao ,  Ronaldus Johannes Gijsbertus Goossens ,  Jun Ye ,  James Patrick Koonmen

IPC: G06F17/50 ,  G03F7/00 ,  B29C64/386 ,  G03F7/20

Abstract: Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.

公开(公告)号：US09672301B2

公开(公告)日：2017-06-06

申请号：US14246961

申请日：2014-04-07

Applicant: ASML NETHERLANDS B.V.

Inventor： Yu Cao ,  Wenjin Shao ,  Jun Ye ,  Ronaldus Johannes Gijsbertus Goossens

IPC: G06F17/50 ,  G03F1/00 ,  G03F1/44 ,  G03F7/20 ,  G06F17/10 ,  G03F1/68

CPC classification number: G06F17/50 ,  G03F1/14 ,  G03F1/44 ,  G03F1/68 ,  G03F7/70433 ,  G03F7/705 ,  G06F17/10 ,  G06F17/5009

Abstract: The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.