公开(公告)号：IN2966DEN2012A

公开(公告)日：2015-07-31

申请号：IN2966DEN2012

申请日：2012-04-09

Applicant: ATI TECHNOLOGIES ULC

Inventor： TOPACIO RODEN R ,  LOW YIP SENG

IPC: H01L21/60

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads.

公开(公告)号：WO2012134710A8

公开(公告)日：2012-12-06

申请号：PCT/US2012027631

申请日：2012-03-03

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES INC ,  TOPACIO RODEN R ,  SU MICHAEL Z ,  MCLELLAN NEIL

Inventor： TOPACIO RODEN R ,  SU MICHAEL Z ,  MCLELLAN NEIL

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02233 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip (15) that has a first conductor pad (85) and a passivation structure (45). A second conductor pad (120) is fabricated around but not in physical contact with the first conductor pad (85) to leave a gap (125). The second conductor pad (120) is adapted to protect a portion of the passivation structure (45).

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供了一种制造方法，其包括提供具有第一导体焊盘（85）和钝化结构（45）的半导体芯片（15）。 围绕第二导体焊盘（85）制造第二导体焊盘（120）而不与第一导体焊盘（85）物理接触以留下间隙（125）。 第二导体焊盘（120）适于保护钝化结构（45）的一部分。

公开(公告)号：WO2008026077A3

公开(公告)日：2011-03-03

申请号：PCT/IB2007003615

申请日：2007-08-31

Applicant: ATI TECHNOLOGIES ULC ,  MCLELLAN NEIL R ,  CHAN VINCENT K ,  TOPACIO RODEN R

Inventor： MCLELLAN NEIL R ,  CHAN VINCENT K ,  TOPACIO RODEN R

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/48

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An integrated circuit package includes an encapsulant retention structure located adjacent to a die on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the die. The retention structure placed on the substrate may also serve as a substrate stiffener to maintain mechanical properties of the substrate, allowing use of a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener allows passive electronic components to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, where a larger strip with a plurality of integrated circuit packages is produced industrially and then singulated.

Abstract translation: 集成电路封装包括邻近衬底上的管芯的密封剂保留结构。 该结构允许更大量的密封剂的放置和保持在模具下渗出。 放置在衬底上的保持结构也可以用作衬底加强件，以保持衬底的机械性能，从而允许使用更理想的更薄衬底。 在一个实施例中，在加强件中使用开口和凹槽允许无源电子部件在使用更薄的衬底时保持机械性能。 使用保留壁或加强件允许使用带状矩阵来制造这些集成电路封装，其中具有多个集成电路封装的较大条带在工业上制造然后被分割。

公开(公告)号：WO2013032956A3

公开(公告)日：2013-09-12

申请号：PCT/US2012052408

申请日：2012-08-25

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES INC ,  TOPACIO RODEN R ,  MCLELLAN NEIL

Inventor： TOPACIO RODEN R ,  MCLELLAN NEIL

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/115 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/06 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing semiconductor chip (15) solder bump (35, 35') and under bump metallisation (UBM) (60, 60') structures and a corresponding device are disclosed. The method includes depositing a first layer (85, 235) of a first metallic material on a semiconductor chip (15) and a second layer (190) of a second metallic material on the first layer (85, 235) of the first metallic material. The first and second layers (85, 235), (190) are reflowed to form a solder structure (35, 35') with a desired ratio of the first metallic material to the second metallic material. In this way, a solder bump of desired composition may be formed without resort to bulk plating of pre-combined solder constituents where variations in solder composition after plating can lead to higher than anticipated reflow temperatures.

Abstract translation: 公开了制造半导体芯片（15）焊料凸块（35,35'）和凸块下金属化（UBM）（60,60'）结构和相应装置的方法。 该方法包括在第一金属材料的第一层（85,235）上沉积第一金属材料的第一层（85,235）和半导体芯片（15）上的第二金属材料层（190） 。 第一和第二层（85,235），（190）被回流以形成具有所需比率的第一金属材料与第二金属材料的焊料结构（35,35'）。 以这种方式，可以形成所需组成的焊料凸块，而不需要大量电镀预组合的焊料成分，其中电镀后焊料组成的变化可导致高于预期的回流温度。

公开(公告)号：EP2380194A4

公开(公告)日：2013-10-02

申请号：EP09832791

申请日：2009-12-18

Applicant: ATI TECHNOLOGIES ULC

Inventor： MARTINEZ LIANE ,  TOPACIO RODEN R ,  LOW YIP SENG

IPC: H01L23/485 ,  H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H01L25/065

CPC classification number: G06F17/5068 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/85181 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/92127 ,  H01L2224/92163 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2224/11 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

公开(公告)号：EP2476135A4

公开(公告)日：2013-05-29

申请号：EP10814842

申请日：2010-09-09

Applicant: ATI TECHNOLOGIES ULC

Inventor： TOPACIO RODEN R ,  LOW YIP SENG

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L23/49838 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/05624 ,  H01L2924/01039 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

公开(公告)号：EP2084739A4

公开(公告)日：2012-02-29

申请号：EP07825728

申请日：2007-08-31

Applicant: ATI TECHNOLOGIES ULC

Inventor： MCLELLAN NEIL R ,  CHAN VINCENT K ,  TOPACIO RODEN R

IPC: H01L23/16 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An integrated circuit package includes an encapsulant retention structure located adjacent to a die on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the die. The retention structure placed on the substrate may also serve as a substrate stiffener to maintain mechanical properties of the substrate, allowing use of a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener allows passive electronic components to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, where a larger strip with a plurality of integrated circuit packages is produced industrially and then singulated.