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公开(公告)号:IN2966DEN2012A
公开(公告)日:2015-07-31
申请号:IN2966DEN2012
申请日:2012-04-09
Applicant: ATI TECHNOLOGIES ULC
Inventor: TOPACIO RODEN R , LOW YIP SENG
IPC: H01L21/60
Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads.
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2.FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT 审中-公开
Title translation: FACE-TO-FACE(F2F)混合用于集成电路公开(公告)号:EP2380194A4
公开(公告)日:2013-10-02
申请号:EP09832791
申请日:2009-12-18
Applicant: ATI TECHNOLOGIES ULC
Inventor: MARTINEZ LIANE , TOPACIO RODEN R , LOW YIP SENG
IPC: H01L23/485 , H01L21/48 , H01L21/60 , H01L23/498 , H01L25/065
CPC classification number: G06F17/5068 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2224/02313 , H01L2224/02331 , H01L2224/0239 , H01L2224/0333 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05644 , H01L2224/05647 , H01L2224/1134 , H01L2224/11462 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/14135 , H01L2224/14136 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48599 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/73207 , H01L2224/81121 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/85181 , H01L2224/85424 , H01L2224/85439 , H01L2224/92127 , H01L2224/92163 , H01L2224/94 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06568 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/01024 , H01L2224/11 , H01L2224/131 , H01L2924/00013 , H01L2924/00 , H01L2924/00012
Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.
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3.SEMICONDUCTOR CHIP WITH STAIR ARRANGEMENT BUMP STRUCTURES 审中-公开
Title translation: 与聚能STAIR SHOCK ARRANGED结构半导体芯片公开(公告)号:EP2476135A4
公开(公告)日:2013-05-29
申请号:EP10814842
申请日:2010-09-09
Applicant: ATI TECHNOLOGIES ULC
Inventor: TOPACIO RODEN R , LOW YIP SENG
IPC: H01L23/485 , H01L21/60
CPC classification number: H01L23/49838 , H01L23/3192 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/81 , H01L2224/0345 , H01L2224/0346 , H01L2224/03612 , H01L2224/03614 , H01L2224/0401 , H01L2224/05018 , H01L2224/05024 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05558 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/1146 , H01L2224/1147 , H01L2224/13111 , H01L2224/16237 , H01L2224/2919 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/3512 , H01L2924/35121 , H01L2224/05624 , H01L2924/01039 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
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4.A METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS 有权
Title translation: VERFAHREN ZUR HERSTELLUNG馄饨基质麻省理工学院AUFBAUSCHICHTEN公开(公告)号:EP2460393A4
公开(公告)日:2015-03-04
申请号:EP10803777
申请日:2010-07-28
Applicant: ATI TECHNOLOGIES ULC
Inventor: LEUNG ANDREW , TOPACIO RODEN , MARTINEZ LIANE , LOW YIP SENG
IPC: H05K3/00 , H01L23/12 , H01L23/488 , H05K1/02 , H05K3/10
CPC classification number: H01L23/49822 , B32B37/02 , B32B2309/105 , B32B2310/0843 , B32B2457/00 , H01L21/4857 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15311 , H05K3/0035 , H05K3/0055 , H05K3/4602 , H05K3/4644 , H05K2201/09136 , Y10T29/49117 , Y10T156/10 , H01L2224/05599
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